Features: Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation¤ BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,etc.¤ COP: BISYNC, DDCMP¤ ASYNC: 5-8 bits plus optional parit Four character receiver and transmitter FIFOsPinoutSpecifications SY...
SCN68562: Features: Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation¤ BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,etc.¤ COP: BISYNC, DDCMP¤ ASYNC: 5-8 ...
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SYMBOL |
PARAMETER |
RATING |
UNIT |
TA |
Operating ambient temperature2 |
0 to +70 |
|
TSTG |
Storage Temperature |
-65 to +150 |
|
VCC |
voltage from VCC to GND3 |
-0.5 to +7.0 |
V |
VS |
Voltage from any pin to ground3 |
-0.5 to V CC+0.5 |
V |
The Philips Semiconductors SCN68562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte couand byte control) synchronous data link controls as well as asynchronous protocols. The SCN68562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers The operating mode and data format of each channel can be programmed independently.
Each channel SCN68562 consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provide 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem control outputs are provided. These inputs and outputs can be optionally programmed for other functions.