Features: Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation¤ BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,etc.¤ COP: BISYNC, DDCMP¤ ASYNC: 5-8 bits plus optional paritFour character receiver and transmitter FIFOs0 to 4Mbit/sec data rateProgram...
SCN26562: Features: Dual full-duplex synchronous/asynchronous receiver and transmitter Multiprotocol operation¤ BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,etc.¤ COP: BISYNC, DDCMP¤ ASYNC: 5-8 ...
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SYMBOL |
PARAMETER |
RATING |
UNIT |
TA |
Operating ambient temperature2 |
0 to +70 |
|
TSTG |
Storage temperature |
-65 to +150 |
|
VCC |
voltages from VCC to GND3 |
-0.5 to +7.0 |
V |
VS |
Voltage from any pin to ground3 |
-0.5 to V CC+0.5 |
V |
The Philips Semiconductors SCN26562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte countand byte control) synchronous data link controls as well as asynchronous protocols. The SCN26562 interfaces to synchronous bus MPUs and is capable of program-polled, interrupt driven, block-move or DMA data transfers.
The operating mode and data format of each channel SCN26562 can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multi-function counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously.
Theoperating rate for the receiver and transmitter of each channel SCN26562 can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem control outputs (RTS and two general purpose) are provided. Because the modem control inputs and outputs are general purpose in nature, they can be optionally programmed for other functions.
This document contains the electrical specifications for the SCN26562. See SCN26562/SCN68562 User!fls Guide for complet functional description.