Features: ` Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mode Operation` Sub 1-V Operable` Max tpd of 1.9 ns at 1.8 V` Low Powe...
SCES388H: Features: ` Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Iof...
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This single positive-edge-triggered D-type flip-flop SCES388H is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This SCES388H is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.