SCES388H

Features: ` Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Ioff Supports Partial-Power-Down Mode Operation` Sub 1-V Operable` Max tpd of 1.9 ns at 1.8 V` Low Powe...

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SeekIC No. : 004485935 Detail

SCES388H: Features: ` Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation` Iof...

floor Price/Ceiling Price

Part Number:
SCES388H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/18

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Product Details

Description



Features:

` Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages
` Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
` Ioff Supports Partial-Power-Down Mode Operation
` Sub 1-V Operable
` Max tpd of 1.9 ns at 1.8 V
` Low Power Consumption, 10-A Max ICC
` ±8-mA Output Drive at 1.8 V
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Protection Exceeds JESD 22
    − 2000-V Human-Body Model (A114-A)
    − 200-V Machine Model (A115-A)
    − 1000-V Charged-Device Model (C101)



Pinout

  Connection Diagram


Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . −0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . .  . . . −0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
          (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . −0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . .. . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, JA (see Note 2): DBV package . . . . . . . . . . . 206°C/W
                                                                           DCK package . . . .. . . . . . . 252°C/W
                                                                           YEA/YZA package .. . . . . . . 154°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . .. . . −65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.



Description

This single positive-edge-triggered D-type flip-flop SCES388H is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This SCES388H is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.




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