SCC68070

The SCC68070 is a 16/32-bit central processing unit suitable for use in a large variety of applications.It is fully object code compatible with the 68000.By integrating standard and advanced peripheral functions on the SCC68070, system costs are drastically reduced.The internal architecture is built around a bus interconnecting the CPU and the various on-chip peripheral functions. Each function has several dedicated connections to the external circuitry. The SCC68070 includes powerful programmable interrupt processing circuitry for interrupts generated by internal and external sources. An on-chip clock generator provides a half crystal frequency clock signal for CPU and peripheral interfaces.

Features of the SCC68070 are:(1)CMOS technology; (2)32-bit internal structure; (3)enhanced bus error handling; (4)4 decoded interrupt inputs; (5)2 programmable interrupt inputs; (6)decoded interrupt acknowledge; (7)built-in clock generator--maximum 35 MHz crystal; (8)on-chip MMU; supporting virtual memory; (9)2-channel DMA controller; (10)12C serial bus interface; (11)UART serial bus interface; (12)16-bit timer/counter; (13)two 16-bit match/count/capture registers; (14)fully 68000 object code compatible; (15)bus interface similar to 68000; (16)56 powerful instruction types; (17)5 basic data types; (18)16 Mbyte addressing range; (19)14 addressing modes; (20)memory mapped I/O; (21)vectored and auto-vectored interrupts; (22)7 interrupt levels; (23)maximum internal clock frequency: 175 MHz; (24)84-pin PLCC or a 120-pin QFP package.

The absolute maximum ratings of the SCC68070 can be summarized as:(1)supply,output current:±10mA;(2)storage temperature range:-55 to 150;(3)operating ambient temperature range:0 to 70;(4)total power dissipation:2W;(5)input voltage on any pin with respect to ground:-0.3V.When a valid bus transfer request is received from a device, the DMA controller will arbitrate for and acquire the bus. The DMA controller indicates to the CPU that it wants to become bus master by generating an internal bus request signal, and the CPU responds by sending an internal bus grant signal, daisy-chained through the DMA controller. It is not offered to the external devices because the DMA controller has a request pending. If BGN has already been offered to the external devices when a DMA request arrives, the DMA controller waits for BGACKN to become inactive.