SAA7114H

1.1 Video decoder

` Six analog inputs, internal analog source selectors, e.g. 6 * CVBS or (2 * Y/C and 2 * CVBS) or (1 * Y/C and 4 * CVBS)
` Two analog preprocessing channels in differential CMOS style inclusive built-in analog anti-alias filters
` Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel
` Automatic Clamp Control (ACC) for CVBS, Y and C
` Switchable white peak control
` Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the expansion port
` On-chip line-locked clock generation according "ITU 601"
` Digital PLL for synchronization and clock generation from all standards and non-standard video sources e.g. consumer grade VTR
` Requires only one crystal (32.11 or 24.576 MHz) for all standards
` Horizontal and vertical sync detection
` Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards
` Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC 4.43 and SECAM
` Adaptive 2/4-line comb filter for two dimensional chrominance/luminance separation
Increased luminance and chrominance bandwidth for all PAL and NTSC standards
Reduced cross colour and cross luminance artefacts
` PAL delay line for correcting PAL phase errors
` Independent Brightness Contrast Saturation (BCS) adjustment for decoder part
` User programmable sharpness control
` Independent gain and offset adjustment for raw data path.

1.2 Video scaler

` Horizontal and vertical down-scaling and up-scaling to randomly sized windows
` Horizontal and vertical scaling range: variable zoom to ^1/64 (icon); it should be noted that the H and V zoom are restricted by the transfer data rates
` Anti-alias and accumulating filter for horizontal scaling
` Vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6-bit phase accuracy)
` Horizontal phase correct up and down scaling for improved signal quality of scaled data, especially for compression and video phone applications, with 6-bit phase accuracy (1.2 ns step width)
` Two independent programming sets for scaler part, to define two 'ranges' per field or sequences over frames
` Fieldwise switching between decoder part and expansion port (X-port) input
` Brightness, contrast and saturation controls for scaled outputs.

1.3 Vertical Blanking Interval (VBI) data decoder and slicer

` Versatile VBI-data decoder, slicer, clock regeneration and byte synchronization e.g. for World Standard Teletext (WST), North-American Broadcast Text System (NABTS), close caption, Wide Screen Signalling (WSS) etc.

1.4 Audio clock generation

` Generation of a field locked audio master clock to support a constant number of audio clocks per video field
` Generation of an audio serial and left/right (channel) clock signal.

1.5 Digital I/O interfaces

` Real-time signal port (R port), inclusive continuous line-locked reference clock and real-time status information supporting RTC level 3.1 (refer to external document "RTC Functional Specification" for details)
` Bi-directional expansion port (X-port) with half duplex functionality (D1), 8-bit YUV
Output from decoder part, real-time and unscaled
Input to scaler part, e.g. video from MPEG decoder (extension to 16-bit possible)
` Video image port (I-port) configurable for 8-bit data (extension to 16-bit possible) in master mode (own clock), or slave mode (external clock), with auxiliary timing and hand shake signals
` Discontinuous data streams supported
` 32-word * 4-byte FIFO register for video output data
` 28-word * 4-byte FIFO register for decoded VBI output data
` Scaled 4 : 2 : 2, 4 : 1 : 1, 4 : 2 : 0, 4 : 1 : 0 YUV output
` Scaled 8-bit luminance only and raw CVBS data output
` Sliced, decoded VBI-data output.

1.6 Miscellaneous

` Power-on control
` 5 V tolerant digital inputs and I/O ports
` Software controlled power saving standby modes supported
` Programming via serial I²C-bus, full read-back ability by an external controller, bit rate up to 400 kbits/s
` Boundary scan test circuit complies with the "IEEE Std. 1149.b1 - 1994".

The SAA7114H is a video capture device for applications at the image port of VGA controllers.

The SAA7114H is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder containing two-dimensional chrominance/luminance separation by an adaptive comb filter and a high performance scaler, SAA7114H including variable horizontal and vertical up and down scaling and a brightness, contrast and saturation control circuit.

SAA7114H is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7114H accepts as analog inputs CVBS or S-video (Y/C) from TV or VCR sources, including weak and distorted signals. An expansion port (X-port) for digital video (bi-directional half duplex, D1 compatible) is also supported to connect to MPEG or video phone codec. At the so called image port (I-port) the SAA7114H supports 8 or 16-bit wide output data with auxiliary reference data for interfacing to VGA controllers.

The target application for SAA7114H is to capture and scale video images, to be provided as digital video stream through the image port of a VGA controller, for display via VGA's frame buffer, or for capture to system memory.

In parallel SAA7114H incorporates also provisions for capturing the serially coded data in the vertical blanking interval (VBI-data). Two principal functions are available:
1. To capture raw video samples, after interpolation to the required output data rate, via the scaler
2. A versatile data slicer (data recovery) unit.

SAA7114H incorporates also a field locked audio clock generation. This function ensures that there is always the same number of audio samples associated with a field, or a set of fields. SAA7114H prevents the loss of synchronization between video and audio, during capture or playback.

The SAA7114H is I2C-bus controlled (full write/read capability for all programming registers, bit rate up to 400 kbits/s).