SA-110

Features: The Intel® StrongARM® SA-110 Microprocessor (SA-110), the first member of the StrongARM® family of high-performance, low-power microprocessors, is optimized for meeting embedded consumer application and portable application requirements. Offering power-saving features, low co...

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SeekIC No. : 004483513 Detail

SA-110: Features: The Intel® StrongARM® SA-110 Microprocessor (SA-110), the first member of the StrongARM® family of high-performance, low-power microprocessors, is optimized for meeting embedde...

floor Price/Ceiling Price

Part Number:
SA-110
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

The Intel® StrongARM® SA-110 Microprocessor (SA-110), the first member of the StrongARM® family of high-performance, low-power microprocessors, is optimized for meeting embedded consumer application and portable application requirements. Offering power-saving features, low cost, and high performance and price/performance, the SA-110 is a solution for high-bandwidth network switching, intelligent office machines, storage systems, and internet appliances, as well as digital cameras, barcode scanners, and other emerging consumer applications. In addition, to delivering performance requirements in a low-power design, the SA-110 offers compatibility with existing ARM™development tools and operating systems.

` High performance
-115 Dhrystone 2.1 MIPS @ 100 MHz
-185 Dhrystone 2.1 MIPS @ 160 MHz
-192 Dhrystone 2.1 MIPS @ 166 MHz
-230 Dhrystone 2.1 MIPS @ 200 MHz
-268 Dhrystone 2.1 MIPS @ 233 MHz
` 144-pin thin quad flat pack (TQFP)
` Low power
-<300 mW @1.65 V/100 MHz
-<450 mW @1.65 V/160 MHz
-<700 mW @2.0 V/166 MHz
-<900 mW @2.0 V/200 MHz
-<1000 mW @2.0 V/233 MHz
` 32-way set-associative caches
-16 Kbyte instruction cache
-16 Kbyte write-back data cache
` Internal phase-locked loop (PLL)
-3.68- or 3.56-MHz oscillator
` 32-entry MMUs
-Maps 4 Kbyte, 64 Kbyte, or 1 Mbyte
` Power-management features
-Idle (power-down) mode
-Sleep (power-down) mode
` Write buffer
-8-entry, 16 bytes each
` Big and little endian operating modes n Memory bus
-Asynchronous or synchronous
-0-33 MHz @ 100 MHz
-0-53 MHz @ 160 MHz
-0-53 MHz @ 166 MHz
-0-66 MHz @ 200 MHz
-0-66 MHz @ 233 MHz
` 3.3-V I/O interface




Description

The SA-110 is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache (Icache); a 16 Kbyte write-back data cache (Dcache); a write buffer; and a memory-management unit (MMU) combined in a single component. The five-stage pipeline distributes tasks evenly over time to remove bottlenecks, ensuring high throughput for the core logic. The SA-110 on-chip MMU supports a conventional two-level page-table structure, with a number of extensions. These features of SA-110 result in a high instruction throughput and real-time response for a small and cost-effective microprocessor.




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