DescriptionThe S75PL127J is a 128 M bit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 M words.The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass com¬mand sequ...
S75PL127J: DescriptionThe S75PL127J is a 128 M bit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 M words.The unlock bypass feature allows the system to program data to...
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DescriptionThe S75PL127JCEBAWB2 is one member of the S75PL127J series. The S75PL127J is a 128 M bi...
The S75PL127J is a 128 M bit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 M words.The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass com¬mand sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode.
Features of the S75PL127J are: (1)provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices; (2)suspends an erase operation to allow read or program operations in other sectors of same bank; (3)hardware method to reset the device to reading array data; (4)a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password.
The absolute maximum ratings of the S75PL127J can be summarized as:(1) VCC: 0.5 V to +4.0 V;(2)storage temperature range:-65 to 150;(3) RESET#: 0.5 V to +13.0 V;(4) output short circuit current: 200 mA;(5) ambient temperature with power applied:65°C to +125.The Simultaneous Read/Write architecture provides simultaneous operationby dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time).Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence.