S5920

The AMCC S5920 was developed to provide the designer with a single multi-function device offering a flexible and easy means to connect applications to the PCI Local Bus. Designers connecting to the PCI Local Bus through the S5920 eliminate the necessity to understand complex PCI Bus timing requirements and the time consuming task of assuring PCI specification compliance. The S5920's design incorporates years of design experience and system knowledge achieved through the popular S5933 PCI Matchmaker device.

The S5920 converts complex PCI bus signals into an easy-to-use 8-, 16- or 32-bit user bus referred to as the Add-On Local Bus. The S5920 Add-On signal pins, shown in Figure 2, provide the designer with a much simpler bus structure in which to interface I/O, memory or data acquisition applications and to port existent ISA-based designs over to the PCI Bus. The bus can be operated either synchronously or asynchronously to the PCI Local Bus with user definable clock speeds from 8 to 40 MHz.

Since the S5920 is a PCI 'Target' or 'Slave' device only, its cost is significantly less than PCI Bus Master solutions making it ideal for low cost applications. The S5920 is compliant with the PCI Local Bus Specification Revision 2.2. It is capable of 132 Mbytes/sec data transfer rates and supports both burst and single DWORD data transfers. The S5920 logic core is powered from a single 5 volt supply and utilizes advanced AMCC technology to achieve low system power consumption at clock speeds to 33 MHz. The S5920 block diagram is shown in Figure 1.

The S5920's superior feature set offers the designer multiple hardware and software design options for higher performance. Up to four Host bus memory or I/O space definable blocks, referred to as Pass-Thru regions, may be implemented providing multiple data channels. Data transfers via a Pass-Thru data channel can be performed through a single buffered to the application or through burstable FIFOs. Added read prefetch and programmable FIFO wait state features allow the user to fine tune system performance. The Pass-Thru data channels also supports an 'active or passive' mode bus interface. Passive mode requires the designer to transfer data by externally driving data onto the Add-On Bus. Active mode minimizes design components by enabling internal logic to drive or acquire the Add-On Bus for reading or writing data independently. Active mode also supports programmable wait state generation for slower Add-On designs.