S4503

Features: • Multiplies input reference frequency by integers 232• Digitally programmable output clock frequencies from 10 MHz to 300 MHz• Two (2) groups of independent clock outputs One group consists of differential PECL outputs One group is a pair of TTL outputs• Propriet...

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S4503 Picture
SeekIC No. : 004482383 Detail

S4503: Features: • Multiplies input reference frequency by integers 232• Digitally programmable output clock frequencies from 10 MHz to 300 MHz• Two (2) groups of independent clock output...

floor Price/Ceiling Price

Part Number:
S4503
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/7

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Product Details

Description



Features:

• Multiplies input reference frequency by integers 232
• Digitally programmable output clock frequencies from 10 MHz to 300 MHz
• Two (2) groups of independent clock outputs
One group consists of differential PECL outputs
One group is a pair of TTL outputs
• Proprietary TTL output drivers with:
Complementary 24 mA peak outputs,source and sink
Source series termination
Edge rates less than 1.5 ns
• Low 250 ps reference typ clock jitter (PECL outputs), 400 ps max
• 1.1 mW or less power dissipation, frequency and load dependent
• 150 MHz to 300 MHz phase-locked loop VCO frequency range
• Advanced BiCMOS process technology
• Space saving 28 PLCC package



Pinout

  Connection Diagram


Specifications

Storage Temperature.................... -55°C to +150°C
VCC Potential to Ground ..................... -0.5V to +7.0V
Input Voltage .......................................-0.5V to +VCC
Static Discharge Voltage ............................... >1750V
Maximum Junction Temperature ................... +130°C
Latch-up Current ......................................... >200 mA
Operating ambient temperature .........0°C to +70°C



Description

The S4503 is a clock synthesizer which utilizes phase-locked loop technology to provide two (2) independently selectable output frequencies in the 10 MHz to 300 MHz range. A reference input may be provided by either a low cost crystal or a TTL frequency source.

The first of the two (S4503) output frequency groups consists of a pair of differential PECL (Positive referenced ECL) outputs which will operate up to 300 MHz. The second group (TTL) consist of two outputs with selectable frequency, up to 80 MHz.

The final frequency of S4503 for each group is digitally selected via three programmable counters. One counter is used to set the internal VCO frequency between 150 MHz to 300 MHz, and the others are used to divide the VCO frequency from 2 thru 16 (TTL) and 1, 2 or 4 (PECL).

All phase-locked loop elements of S4503 are provided on chip with the exception of the passive components needed for the loop filter function and VCO.




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