S4406

Features: • Generates outputs from 10 MHz to 66 MHz• Four groups of three outputs (12 outputs total)• Eight user-selectable output functions for each group• TTL compatible outputs, with <1.5-ns edge rates• Performs clock doubling, dividing, invert, lead/lag placeme...

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SeekIC No. : 004482381 Detail

S4406: Features: • Generates outputs from 10 MHz to 66 MHz• Four groups of three outputs (12 outputs total)• Eight user-selectable output functions for each group• TTL compatible ou...

floor Price/Ceiling Price

Part Number:
S4406
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• Generates outputs from 10 MHz to 66 MHz
• Four groups of three outputs (12 outputs total)
• Eight user-selectable output functions for each group
• TTL compatible outputs, with <1.5-ns edge rates
• Performs clock doubling, dividing, invert, lead/lag placement
• Internal VCO running between 160 to 266 MHz
• 1.0m BiCMOS technology
• Output skew less than 500 ps
• 52 PQFP package



Application

• High-performance microprocessor systems
• CMOS ASIC systems
• Backplane clock deskew and distribution
• Compatible with Intel's Pentium™ processor



Pinout

  Connection Diagram


Specifications

TTL Supply Voltage VCC (VEE = 0) 7.0 V
TTL Input Voltage (VEE = 0) 5.5 V
Operating Temperature 0°C to 70°C ambient
Operating Junction Temperature TJ + 130°C
Storage Temperature 65°C to +150°C



Description

The S4406 BiCMOS clock generator provides 12 TTL outputs with less than 500 ps of skew. Implemented in AMCC's 1.0m BiCMOS technology, the internal PLL and divider/delay selector logic allow the user to individually tailor the (4) TTL output groups to the system's needs. The internal VCO can operate between 160 to 266 MHz, and the programmability allows the user to generate output clocks in the 2066 MHz range.

The S4406 offers the user the ability to select the appropriate phase and frequency relationship for each of the four groups of three TTL clock outputs.

In addition to clock doubling and inversion functions, the S4406 allows any output groups to lead or lag the others by the minimum phase delay of 3.756.25 ns.




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