Features: Architecture
` Integrated system for hand-held devices and general embedded applications.
` 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core.
` Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux.
` Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main
memory bandwidth and latency on performance.
` ARM920T CPU core supports the ARM debug architecture and has a Tracking ICE mode.
` Internal AMBA(Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
System Manager
` Little/Big Endian support.
` Address space: 32M bytes for each bank (Total 256Mbyte)
` Supports programmable 8/16/32-bit data bus width for each bank.
` Fixed bank start address and programmable bank size for 7 banks.
` Programmable bank start address and bank size for one bank.
` 8 memory banks.
- 6 memory banks for ROM, SRAM etc.
- 2 memory banks for ROM/SRAM/DRAM(EDO or Synchronous DRAM)
` Fully Programmable access cycles for all memory banks.
` Supports external wait signal to expend the bus cycle.
` Supports self-refresh mode in DRAM/SDRAM for power-down.
` Supports asymmetric/symmetric address of DRAM.
Cache Memory
` 64 way set-associative cache with I-Cache(16KB) and D-Cache(16KB).
` 8-words per line with one valid bit and two dirty bits per line
` Pseudo random or round robin replacement algorithm.
` Write through or write back cache operation to update the main memory.
` The write buffer can hold 16 words of data and four address.
Clock & Power Manager
` Low power
` The on-chip MPLL and UPLL UPLL makes the clock for operating USB Host/Device. MPLL makes the clock
for operating MCU at maximum 150Mhz @ 1.8V.
` Clock can be fed selectively to each function block by software.
` Power mode: Normal, Slow, Idle, Stop mode and SL_IDLE mode. Normal mode: Normal operating mode.
Slow mode: Low frequency clock without PLL. Idle mode: Stop the clock for only CPU. Stop mode: All clocks
are stopped. SL_IDLE mode: All clocks except LCD are stopped.
` Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode.
Interrupt Controller
` 32 Interrupt sources (Watch dog timer, 5Timer, 6UART, 8External interrupts, 4 DMA, 2 RTC, 1 ADC, 1 IIC, 1
SPI, 1 MMC, 2 USB)
` Level/Edge mode on external interrupt source.
` Programmable polarity of edge and level.
` Supports FIQ (Fast Interrupt request) for very urgent interrupt request.
Timer with PWM (Pulse Width Modulation)
` 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation
` Programmable duty cycle, frequency, and polarity
` Dead-zone generation.
` Supports external clock source.
RTC (Real Time Clock)
` Full clock feature: msec, sec, min, hour, day, week, month, year.
` 32.768 KHz operation.
` Alarm interrupt.
` Time tick interrupt
General Purpose Input/Output Ports
` 8 external interrupt ports
` 90 multiplexed input/output ports
UART
` 2-channel UART with DMA-based or interruptbased operation
` Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive
` Supports H/W handshaking during transmit/receive
` Programmable baud rate
` Supports IrDA 1.0
` Loop back mode for testing
` Each channel has internal 16-byte Tx FIFO and 16-byte Rx FIFO.
DMA Controller
` 4-ch DMA controller.
` Support memory to memory, IO to memory, memory to IO, IO to IO
` Burst transfer mode to enhance the transfer rate.
A/D Converter
` 8-ch multiplexed ADC.
` Max. 500KSPS and 10-bit Resolution.
LCD Controller
STN LCD displays Feature
` Supports 3 types of STN LCD panels ; 4-bit dual scan, 4-bit single scan, 8-bit single scan display type.
` Supports the monochrome, 4 gray levels, 16gray levels, 256 color and 4096 colors for STN LCD.
` Supports multiple screen size
- Typical actual screen size: 640x480, 320x240, 160x160 (pixels)
- Maximum virtual screen size (color mode): 4096x1024, 2048x2048, 1024x4096 etc.
` Supports power saving mode(Enhanced SL_IDLE mode.)
TFT (Thin Film Transistor) color displays Feature
` Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette color displays for color TFT.
` Supports 16 bpp non-palette true-color displays for color TFT.
` Supports maximum 32K (64K using intensity) color TFT at 16 bpp mode.
` Supports multiple screen size
- Typical actual screen size: 720x240, 320x240, 160x160 (pixels)
- Recommended maximum screen size: 640x480 (8 bpp, 32bit SDRAM @80MHz)
- Maximum virtual screen size (16bpp mode): 2048x1024 etc
Watchdog Timer
` 16-bit Watchdog Timer.
` Interrupt request or system reset at time-out.
IIC-BUS Interface
` 1-ch Multi-Master IIC-Bus.
` Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard
mode or up to 400 Kbit/s in the fast mode.
IIS-BUS Interface
` 1-ch IIS-bus for audio interface with DMA-based operation.
` Serial, 8/16bit per channel data transfers.
` Supports IIS format and MSB-justified data format.
USB Host
` 2-port USB Host
` Complies with OHCI Rev. 1.0
` Compatible with the USB Specification version 1.1
USB Device
` 1-port USB Device.
` 5 Endpoints for USB Device.
` Compatible with the USB Specification version 1.1
MMC Interface
` Multi-Media Card Protocol version 2.11 compatible
` 2x16 Bytes FIFO for receive/transmit.
` DMA-based or interrupt-based operation.
SPI Interface
` Serial Peripheral Interface Protocol version 2.11 compatible
` 2x8 bits Shift register for receive/transmit.
` DMA-based or interrupt-based operation.
Operating Voltage Range
` Core: 1.8V
` I/O: 3.3V
Operating Frequency
` Up to 150 MHz
Package
` 208 LQFP/208 FBGAPinout
DescriptionSAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA, System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, 8- channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPI and PLL for clock generation.
The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture)
An outstanding feature of the S3C2400 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with a 8-word line length.
By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip S3C2400 functions that are described in this document include:
` 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, and MMU.
` External memory controller. (EDO/SDRAM Control, Chip Select logic)
` LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA.
` 4-ch DMAs with external request pins
` 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI
` 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller
` MMC interface (ver 2.11)
` 2-port USB Host /1- port USB Device (ver 1.1)
` 4-ch PWM timers & 1-ch internal timer
` Watch Dog Timer
` 90-bit general purpose I/O ports/8-ch external interrupt source
` Power control: Normal, Slow, Idle, Stop and SL_IDLE mode
` 8-ch 10-bit ADC.
` RTC with calendar function.
` On-chip clock generator with PLL
S3C2400 Data Sheet
