S320DM642

The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features of S320DM642 controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets of S320DM642 are a key memory-saving feature, distinguishing the C64x CPUs from other VLIW architectures. The C64x™VelociTI.2™extensions add enhancements to the TMS320C62x™DSP™VelociTI architecture. These enhancements include: