S2104

The S2104 facilitates high-speed serial transmission of data in a variety of applications including Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides four separate transceivers which can be operated individually for a data capacity of >4 Gbps.

Each S2104 bi-directional channel provides parallel to serial and serial to parallel conversion, clock generation/ recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip quad receive PLL is used for clock recovery and data re-timing on the four independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 2.5 watts.

Figure 1 shows the S2104 and S2004 in a Fibre Channel application. Figure 2 combines the S2104 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.