S2002

The S2002 facilitates high-speed serial transmission of data in a variety of applications including Gigabit Ethernet, Fibre Channel, serial backplanes, and proprietary point to point links. The chip provides two separate transceivers which are operated individually for a data capacity of >2 Gbps.

Each bi-directional channel provides 8B/10B coding/ decoding, parallel to serial and serial to parallel conversion, clock generation/recovery, and framing. The on-chip transmit PLL synthesizes the high-speed clock from a low-speed reference. The on-chip dual receive PLL is used for clock recovery and data retiming on the two independent data inputs. The transmitter and receiver each support differential PECL-compatible I/O for copper or fiber optic component interfaces with excellent signal integrity. Local loopback mode allows for system diagnostics. The chip requires a 3.3V power supply and dissipates 1.85 watts.

Figure 1 shows the S2202 and S2002 in a Gigabit Ethernet application. Figure 2 combines the S2002 with a crosspoint switch to demonstrate a serial backplane application. Figure 3 is the input/ output diagram. Figures 4 and 5 show the transmit and receive block diagrams, respectively.