S1D13503F00A2

The S1D13503F00A2 is one member of the S1D13503 series.The transmit channel consists of a digital-to-analog converter and switched-capacitor pulse forming network followed by a differ- ential line driver. The pulse forming network receives symbol data and generates a standard 2B1Q output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion).

Both the backplane bias and the CCFL supply can be shut down independently. When both sections are shut down, supply current drops to 25µA. The LCD contrast and CCFL brightness can be adjusted by clocking sep- arate digital inputs or using external potentiometers. LCD contrast and backlight brightness settings are pre- served in their respective counters while in shutdown. On power-up, the LCD contrast counter and CCFL brightness counter are set to one-half scale. The ICs are powered from a regulated 5V supply. The magnetics are connected directly to the battery, for maximum power efficiency. The CCFL driver uses a Royer-type resonant architec- ture. It can provide from 100mW to 6W of power to one or two tubes. The MAX753 provides a negative LCD bias voltage; the MAX754 provides a positive LCD bias voltage.

S1D13503F00A2 is a smart 8K 8x 8 Serial Electrically Erasable PROM (EEPROM) with a high-speed 1MHz SE2.bus whose protocol is functionally equivalent to the industry-standard I2C bus. This device has been developed for advanced applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-programmable features. The S1D13503F00A2 offers a relocatable 4K-bit block of ultra-high-endurance memory for data that changes frequently. The remain- der of the array, or 60K bits, is rated at 1,000,000 ERASE/WRITE (E/W) cycles guaranteed. The S1D13503F00A2 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. This device also features programmable security options for E/W pro- I and Q channel LVDS Data Outputs that are delayed by one CLK cycle in the output demultiplexer. Compared with the DI/DQ outputs, these outputs represent the earlier time sample. These outputs should always be terminated with a 100 differential resistor.