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RED5/6

Features: • Clock input pulse shaper accepts 50Hz/60Hz sine wave directly• Fully static counter operation• +4.5V to +15V operation (VDD - VSS)• Low power dissipation• High noise immunity• Reset• Input Enable• 50Hz/60Hz division select input• Ou...

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SeekIC No. : 004475916 Detail

RED5/6: Features: • Clock input pulse shaper accepts 50Hz/60Hz sine wave directly• Fully static counter operation• +4.5V to +15V operation (VDD - VSS)• Low power dissipation• H...

RED5/6 Data Sheet

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Part Number:
RED5/6
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/26

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Product Details

Description



Features:

• Clock input pulse shaper accepts 50Hz/60Hz
   sine wave directly
• Fully static counter operation
• +4.5V to +15V operation (VDD - VSS)
• Low power dissipation
• High noise immunity
• Reset
• Input Enable
• 50Hz/60Hz division select input
• Output low power TTL compatible at +4.5V operation
• Square Wave Output (except for ÷ 5)
• RED x/y (DIP); RED x/y-S (SOIC) See Figure 1


Application

Time base generator from either 50Hz or 60Hz line frequency to produce:
-10 pulses per second (RED 5/6)
-1 pulse per second (RED 50/60)
-1 pulse per 2 seconds (RED 100/120)
-1 pulse per .1 minute (RED 300/360)
-1 pulse per 10 seconds (RED 500/600)
-1 pulse per minute (RED 3000/3600)


Pinout

Connection Diagram


Specifications

PARAMETER                             SYMBOL                VALUE             UNIT
Storage Temperature              TSTG                   -65 to +150        °C
Operating Temperature           TA -40 to             +85                    °C
DC Supply Voltage                   (VDD-Vss)           +18                      V
Voltage at any input                VIN Vss               -.3 to VDD +.3      V


Description

The counter of RED5/6 advances by one on each negative transition of the input clock pulse as long as the Enable signal is High and the Reset signal is Low. When the Enable signal is Low the input clock pulses will be inhibited and the counter of RED5/6 will be held at the state it was in prior to bringing the Enable Low. A High Reset signal clears the counter to zero count.

Depending on RED5/6 used, a Low on the Division Select input will cause a Divide by 6, 60, 120, 360, 600 or 3600. A High on the Division Select will cause a Divide by 5, 50, 100, 300, 500 or 3000.




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