Features: RC32300 32-bit CPU core 32-bit MIPS instruction set Supports big or little endian operation MMU 16-entry TLB Supports variable page sizes and enhanced write algorithm Supports variable number of locked entries 8KB Instruction Cache 2-way set associative LRU replacement algorithm 4 word ...
RC32365: Features: RC32300 32-bit CPU core 32-bit MIPS instruction set Supports big or little endian operation MMU 16-entry TLB Supports variable page sizes and enhanced write algorithm Supports variable nu...
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Symbol | Parameter | Min1 | Max1 | Unit |
VCCI/O | I/O Supply Voltage | -0.6 | 4.0 | V |
VCCCore | Core Supply Voltage | -0.3 | 3.0 | V |
VCCPLL | PLL Supply Voltage | -0.3 | 3.0 | V |
Vimin | Input Voltage - undershoot | -0.6 | - | V |
Vi | I/O Input Voltage | Gnd | VCCI/O+0.6 | V |
Ta, Industrial |
Ambient Operating Temperature |
-40 | +85 | |
Ta, Commercial |
Ambient Operating Temperature |
0 | +70 | |
Tstg | Storage Temperature | -40 | +125 |
The following table lists the functions of the pins provided on the RC32365. Some of the functions listed may be multiplexed onto the same pin indicated as alternate functions).
To define the active polarity of a signal, a suffix will be used. Signals ending with an "N" should be interpreted as being active, or asserted, when at logic zero (low) level. All other signals (including clocks, buses, and select lines) of RC32365 will be interpreted as being active, or asserted, when at a logic one high) level.