R2021

The R2021 is designed based on the RDC 16bit RISC architecture high performance microprocessor.It also integrates the function of SDRAM controller, non-multiplexed address bus, interrupt controller, DMA controller, watchdog timer, supports two compatible 16-byte FIFO UART serial channels and programming I/O (PIO) pins and two fast Ethernet MAC (Media Access Controller) on a chip.

The advanced architecture of internal high speed local bus significantly increases the overall system performance. High performance and high integration enable R2021 to significantly reduce the total BOM cost of system, while increasing functionality and performance.