QT117L

      The QT117L is designed to output raw data over a master-mode SPI port which allows a host MCU to seperately process signal data without any pre-processing by the QT117L.For  attention the data is 16-bits and actual binary values depend on both signal load (Cx) and sampling capacitor value(Cs).As Cx rises,the SPI signal value will drop while as Cs rises,the SPI signal will rise.
      The pinouts of the QT117L have been concluded as eight pins.The pin1's function is that the Vcc would be +3 to +5V.The pin2's function is SPI data.The pin3's function is SPI clock.The pin4's function is sync.The pin5's function is SPI frame.The pin6's function is SNS1.The pin7's function is SNS2.The pin8's function is GND.
      Some notes about QT117L.The first is about SPI data that the SPI port outputs 16 bit data and sends them to MSB first.The second one is about the SPI clock.The SPI clock has 16 positive-going clock edges that the user should use them to clock the serial data into a shift register.The third one is about SPI frame.Frame is a negative-going signal that brackets or 'frame' the SPI datastream.The fourth one is about its SPI timing that would timing of all the signals which is 50us from any edge to any other edge among the 3 SPI signals.The fifth one is about the sync that if this pin is tied high,the part will be repeatedly acquire and send SPI data every 70-100ms.The part will be kept in a quiescent mode and consumes only a few microamps if this pin is held low.The sixth one is about the SPI during quiescent state.All three SPI lines are held in a three-state mode during quiescent.This would happens about 50 us after frame goes high following the SPI transmission.The last one is about SNS1 and SNS2.These are the signal sampling pins.The Cs capacitor would be connected accross them.And the signals lead is normally connected to SNS2.