QS5820T

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDD Terminals.
3. All terminals except VDD.

The QS5820T clock driver/buffer circuits can be used for clock distribution schemes where low skew, high speed, and small footprint are primary concerns. The QS5820T offers four banks of five non-inverting outputs. Designed in IDT's proprietary QCMOS process, this device provides low propagation delay buffering with on-chip skew of 0.5ns for same-transition, same-bank signals. The QS5820T provides major skew advantages over octal type devices where total part-to-part skew (tSK( of >1ns is unacceptable. Furthermore, board area consumed by the QVSOP package is almost one-third that of the typical SOIC package offered for octal devices. This clock buffer product is designed for use high performance workstation, multi-board computing and telecommunications systems. The QS5820T is available in the 40-pin QVSOP package which offers the world's smallest logic footprint.