Position: Home  > All Categories> Integrated Circuits (ICs) > QS53806

QS53806

Features: - JEDEC compatible LVTTL inputs and outputs- 10 low skew clock outputs (inverting)- Monitor output- Clock inputs are 5V tolerant- Pinout and function compatible with QS5806- Input hysteresis for better noise margin- Guaranteed low skew· 0.6ns output skew (same bank)· 0.8ns output skew (d...

product image

QS53806 Picture
See larger image
SeekIC No. : 004468512 Detail

QS53806: Features: - JEDEC compatible LVTTL inputs and outputs- 10 low skew clock outputs (inverting)- Monitor output- Clock inputs are 5V tolerant- Pinout and function compatible with QS5806- Input hysteres...

QS53806 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
QS53806
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/11/21

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

-  JEDEC compatible LVTTL inputs and outputs
-  10 low skew clock outputs (inverting)
-  Monitor output
-  Clock inputs are 5V tolerant
-  Pinout and function compatible with QS5806
-  Input hysteresis for better noise margin
-  Guaranteed low skew
·  0.6ns output skew (same bank)
·  0.8ns output skew (different banks)
·  1.5ns part-to-part skew
-  Std. and A speed grades
-  Available in QSOP and SOIC packages


Pinout

Connection Diagram


Specifications

Rating
Symbol
Max
 unit
Supply Voltage Range
V CC1, VCC2
0.5 to +4.6
 V
Input Voltage Range
VI (2)
0.5 to +5.5
 V
Voltage range applied to any
output in the high or low state
VO(2)
0.5 to VDD + 0.5
 V
Input clamp current
IIK (VI < 0)
50
 mA
Terminal Voltage with Respect
to GND (inputs VIH 2.5, VIL 2.5)
IOK
(VO < 0 or VO > VDD)
-50
 mA
Continuous Output Current
IRES
±100
 mA
Continuous Current
VDD or GND
65 to +150
 mA
Junction Temperature
TSTG
150
 °C


NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.




Description

The QS53806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS53806 offers banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with onchip skew of 0.6ns for same-transition, same-bank signals.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Batteries, Chargers, Holders
ICR18650-28A
ICR18650-26F/h
Semiconductor Modules
2DI300A-050-03
7MBR25SA-120-50
Connectors, Interconnects
ASP-134488-01
WM4078-ND
Optical Inspection Equipment
AA924
A21K4B
Switches
US32DMRJ
HBGQ22P-11ET
Resistors
A101G
3006P-1-205LF
View more