QLUM3216-PQ208C

Features: • Implements one Utopia L3 Master and one Utopia L2 Master providing a solution to bridge Utopia Slave devices of different Levels• Compliant with ATM-Forum af-phy-0039.000 (L2) and af-phy-0136.000 (L3) specification• Single chip solution for improved system integration...

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SeekIC No. : 004468156 Detail

QLUM3216-PQ208C: Features: • Implements one Utopia L3 Master and one Utopia L2 Master providing a solution to bridge Utopia Slave devices of different Levels• Compliant with ATM-Forum af-phy-0039.000 (L2...

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Part Number:
QLUM3216-PQ208C
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/9/26

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Product Details

Description



Features:

• Implements one Utopia L3 Master and one Utopia L2 Master providing a solution to bridge Utopia Slave devices of different Levels
• Compliant with ATM-Forum af-phy-0039.000 (L2) and af-phy-0136.000 (L3) specification
• Single chip solution for improved system integration
• Supports 16 Bit busses on both interfaces, single PHY
• Support for cell level transfer mode
• Meets 50MHz performance on Level 2 interface offering up to 800Mbps cell rate transfers
• Cell and clock rate decoupling with on chip FIFOs
• Up to 1.5 KByte of on chip FIFO per data direction
• Integrated management interface and built-in errored cell discard
• ATM Cell size programmable via external pins from 16 to 128 bytes
• Optional Utopia parity generation/checking enable/disable via external pin
• Built in JTAG port (IEEE1149 compliant)
• Simulation model available for system level verification (Contact Quicklogic for details)
• Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches



Pinout

  Connection Diagram


Description

The Utopia (Universal Test & Operations PHY Interface for ATM) interface QLUM3216-PQ208C is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices.

The Utopia Standard of QLUM3216-PQ208C defines a full duplex bus interface with a Master/Slave paradigm. The Slave interface responds to the requests from the Master. The Master performs PHY arbitration and initiates data transfers to and from the Slave device.

The ATM forum of QLUM3216-PQ208C has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps (L2) to 3.2Gbit/s (L3).

The following Table 1 gives an overview of the main differences in these three levels.

Utopia Level 1 of QLUM3216-PQ208C implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16 Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the interface.

In addition to the differences in throughput, Utopia Level 2 of QLUM3216-PQ208C uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (Multi-PHY or MPHY operation). This allows the implementation of aggregation units that multiplex several slave devices to a single Master device. The Level 2 and Level 3 of QLUM3216-PQ208C are pointto- point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion  of multiple slaves, but they must be implemented in a single physical device connected to the Utopia Interface.




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