Q67100-Q1838

• High Performance:

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The HYB Q67100-Q1838 are four bank Synchronous DRAM's organized as 4 banks * 4MBit*4, 4 banks *2 MBit *8 and 4 banks*1 Mbit*16 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefects multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced 0.2 mm 64 MBit DRAM process technology.

The Q67100-Q1838 is designed to comply with all JEDEC standards set for Synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V ± 0.3 V power supply and are available in TSOPII packages.