Q3800B

The Q3800B is designed as BiCMOS logic arrays. AMCC BiCMOS logic arrays combine an advanced 1.5 micron oxide isolated bipolar process with a 1.5 micro CMOS process on a single silicon chio. The N type epitaxial layer serves as the foundation for both the NPN bipolar and CMOS devices.

Q3800B has four features and benefits. The first one is it would have high speed. The next one is it would have high density. The next one is it would have low power. The next one is it would have ECL / TTL capability. That are all the main features.

Some important preliminary product data of Q3800B have been concluded into several points as follow. The first one is about its equivalent gates which would be 3840. The next one is about its number of I/O which would be 106. The next one is about its average cell utilization which would be 90%. The next one is about its max internal F/F toggle frequency which would be typ 175MHz. The next one is about its internal gate delay (typical) 2 loads, 2 mm metal which would be 0.70ns. The next one is about its I/O pair delay (typical) which would be 3.7ns for ECL and would be 7.2ns for TTL single supply +5V and would be 8.0ns for TTL mixed mode +5V to -5.2V. The next one is about its typical power dissipation at 90% utilization, 50% inputs, 50% outputs which would be 2.7W.

The development of AMCC's BiCMOS process was promted by the desire to retain the individual advantages of CMOS's low power and high densities and advanced bipolar technology's high speed and drive capability. AMCC's BiCMOS arrays have CMOS devices for logic implementation only. And therefor, utilize devices sized smaller than those for purely 1.5 micron CMOS array. Because there are no large metal interconnects to drive, the low-power advantages preserved while the density is incresed. And so on. For more information please contact us.