Q24P008

The Q24P008 is designed as logic arrays which combines proven AMCC 1.0 micron BiCMOS logic array technology with an internal phase-locked loop to provide a high perfirmance, low power solution for synchronous clock generation, distribution, and deskewing applications. Its typical applications include clock generation and distribution, frequency synthesis, CMOS ASIC system clock deskewing. The next one is high-speed microprocessor systems and backplane clock deskew and distribution.

Q24P008 has many features. The first one is on-chip phase-locked loop with VCO operating at 160 to 320MHz. The next one is 720 gates of customizable digital logic. The next one is support for up to 10 TTL outputs at up to 80MHz. The next one is support for PECL and ECL outputs up to 210MHz. The next one is TTL outputs have less than 400ps maximum skew (with balanced routing and loading). The next one is utilizes proven Q24000 series macro library. The next one is TTL, CMOS and +5V ECL capability. The next one is speed / power programmable I/O macros. The next one is maximum 1ns of phase error. The next one is up to 100% gate utilization or digital logic. The next one is typical power less than 1W. That are all the main features.

Some performance summary of Q24P008 have been concluded into several points as follow. For the phase-locked loop the first one is about its VCO operating frequency which would be from 160 to 320MHz. The next one is about its maximum phase error which would be 1ns. The next one is about its loop acquisition time which would be typ 500us. The next one is about its input reference frequency range which would be from 10 to 80MHz. That are all the main specifications above. And so on. If you have any question or suggestion or want to know more information please contact us.