PX1041A

The PX1041A is a high-performance, low-power, four-lane PCI Express electrical PHYsical layer (PHY) that handles the low level PCI Express protocol and signaling. The PX1041A PCI Express PHY is compliant to the PCI Express Base Specification, Rev. 1.0a, and Rev. 1.1. The PX1041A includes features such as Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and provides superior performance to the Media Access Control (MAC) layer devices.

The PX1041A is a 2.5 Gbit/s PCI Express PHY with 4 ´ 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data. The 4 ´ 8-bit data interface operates at 250 MHz with SSTL Class I signaling at 2.5 V or 1.8 V. The SSTL signaling is compatible with the I/O interfaces available in FPGA products.

The PX1041A PCI Express PHY supports advanced power management functions. The PX1041AI is for the industrial temperature range (-40 °C to +85 °C).