Features: ` DUAL BANK FLASH MEMORIES 1 Mbit of Primary Flash Memory (8 Uniform Sectors) 256 Kbit Secondary EEPROM (4 Uniform Sectors) Concurrent operation: read from one memory while erasing and writing the other` 16 Kbit SRAM (BATTERY-BACKED)` PLD WITH MACROCELLS Over 3,000 Gates Of PLD: DPLD and...
PSD813F1A-12JI_1105665: Features: ` DUAL BANK FLASH MEMORIES 1 Mbit of Primary Flash Memory (8 Uniform Sectors) 256 Kbit Secondary EEPROM (4 Uniform Sectors) Concurrent operation: read from one memory while erasing and wri...
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` DUAL BANK FLASH MEMORIES
1 Mbit of Primary Flash Memory (8 Uniform Sectors)
256 Kbit Secondary EEPROM (4 Uniform Sectors)
Concurrent operation: read from one memory while erasing and writing the other
` 16 Kbit SRAM (BATTERY-BACKED)
` PLD WITH MACROCELLS
Over 3,000 Gates Of PLD: DPLD and CPLD
DPLD - User-defined Internal chip-select decoding
CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs)
` 27 RECONFIGURABLE I/Os
27 individually configurable I/O port pins that can be used for the following functions: MCU I/Os; PLD I/Os; Latched MCU address output; and Special function I/Os. Note: 16 of the I/O ports may be configured as open-drain outputs.
` ENHANCED JTAG SERIAL PORT
Built-in JTAG-compliant serial port allows full-chip In-System Programmability (ISP)
Efficient manufacturing allows for easy product testing and programming
` PAGE REGISTER
Internal page register that can be used to expand the microcontroller address space by a factor of 256.
` PROGRAMMABLE POWER MANAGEMENT Figure 1. Packages
` HIGH ENDURANCE:
100,000 Erase/WRITE Cycles of Flash Memory
10,000 Erase/WRITE Cycles of EEPROM
1,000 Erase/WRITE Cycles of PLD
Data Retention: 15-year minimum at 90°C (for Main Flash, Boot, PLD and Configuration bits).
` SINGLE SUPPLY VOLTAGE: 5V±10% for 5V
` STANDBY CURRENT AS LOW AS 50A
Symbol |
Parameter |
Min. |
Max. |
Unit |
TSTG |
Storage Temperature |
65 |
125 |
°C |
TLEAD |
Lead Temperature during Soldering (20 seconds max.)1 |
235 |
°C | |
VIO |
Input and Output Voltage (Q = VOH or Hi-Z) |
0.6 |
7.0 |
V |
VCC |
Supply Voltage |
0.6 |
7.0 |
V |
VPP |
Device Programmer Supply Voltage |
0.6 |
14.0 |
V |
VESD |
Electrostatic Discharge Voltage (Human Body model) 2 |
2000 |
2000 |
V |
The PSD813F1A-12JI_1105665 family of Programmable Microcontroller (MCU) Peripherals brings In-System Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU based applications.
PSD813F1A-12JI_1105665 devices integrate an optimized "microcontroller macrocell" logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus and the internal PSD registers to simplify communication between the MCU and other supporting devices.
The PSD813F1A-12JI_1105665 family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board.