PRS5G

• 2.5-Gbps (PRS 5G) and 10-Gbps (PRS 20G) full-duplex user bandwidth switch devices with an overspeed of two towards the backplane
• Embedded IBM 3.2-Gbps SerDes, with 8b/10b coding and XAUI-compliant high-speed serial links
• PRS 5G (PRS C48X): CSIX-L1 or PL3-based (POS-PHY Level 3 / OIFSPI3- 01.0) 32-bit wide interface for multi-GE / OC-48 network processors
• PRS 20G (PRS C192X): CSIX-L1 64-bit wide or 128-bit wide interface for a 10-Gbps / OC-192 network processor or 4x CSIX-L1 or PL3-based (POS-PHY Level 3 / OIF-SPI3-01.0) 32-bit wide interfaces for multi-GE / OC-48 network processors.
• PRS 20G (PRS C192X) operation in subport mode or, in conjunction with the PRS 80G switch core, in quad PRS 5G (PRS C48X) mode, for more integrated line card solutions
• Dual-switch attachment for redundant switch plane operations (central switch configurations)
• Highly-efficient multicast and broadcast mechanism
• Ingress virtual output queuing (VOQ) per destination port and priority, with separate multicast queues, preventing head-of-line blocking
• Up to four levels of traffic priority (CoS) and four programmable ingress queue thresholds (ingress CSIX / PL3 flow control per destination port and priority)
• Packet scheduling: strict priority scheduling, credit table (weighted round-robin), exhaustive highest priority first
• Implements flow control bit map mapping to ease adapter redundancy schemes
• End-to-end packet payload protection, with optional cyclic redundancy check insertion
• Internal loop back support for both the CSIX / PL3 interface and switch interface
• Hardware compatibility with PRS 80G switch core device via SerDes operating at 3.2 Gbps
• Backward compatibility with PRS 64Gu switch core device via SerDes operating at 2.5 Gbps (overspeed factor of 1.6)
• Backward compatibility with PRS Q-64G switch core device via SerDes operating at 2.5 Gbps (overspeed factor of 1.6 for PRS 20G / PRS C192X, or 6.4 for PRS 5G / PRS C48X)