PM7385

`Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit "Any-PHY" Packet Interface (APPI) for transfer of packet data using an external controller.
`Supports up to 672 bi-directional HDLC channels assigned to a maximum of 84 channelised or unchannelised links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface.
`Data on the SBI interface is divided into 3 Synchronous Payload Envelopes (SPEs). Each SPE can be configured independently to carry data for either 28 T1/J1 links, 21 E1 links, or 1 unchannelised DS-3 link.
`Links in an SPE can be configured individually to operate in clear channel mode, in which case, all framing bit locations are assumed to be carrying HDLC data.
`Links in an SPE can be configured individually to operate in channelised mode, in which case, the number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1 links) and from 1 to 31 (for E1 links).
`Supports three bi-directional HDLC channels each assigned to an unchannelised link with arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz. Each link may be configured individually to replace one of the SPEs conveyed on the SBI interface.
`For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
`For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value.
`Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently on the receive APPI. For channelised links, the octets are aligned with the receive time-slots.
`For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
`For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the external controller or automatically when the channel underflows.
`Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from the transmit APPI. For channelised links, the octets are aligned with the transmit time-slots.
`Supports per-channel configurable APPI burst sizes of up to 256 bytes for transfers of packet data.
`The FREEDM maintains packet level performance metrics such as number of received packets, number of received packets with frame check sequence errors, number of transmitted packets, number of receive aborted packets, and number of transmit aborted packets.
`Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and the receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering.
`Provides a 16 bit microprocessor interface for configuration and status monitoring.
`Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
`Supports 3.3 Volt tolerant I/O.
`Low power 2.5 Volt 0.25 m CMOS technology.
`352 pin enhanced ball grid array (SBGA) package.

The PM7385 FREEDM-84A672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing for a maximum of 672 bi-directional channels.

The FREEDM-84A672 PM7385 may be configured to support channelised T1/J1/E1 or unchannelised traffic on up to 84 links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface. The SBI interface transports data in three Synchronous Payload Envelopes (SPEs), each of which may be configured independently to carry either 28 T1/J1 links, 21 E1 links or a single DS-3 link. For channelised T1/J1/E1 links, the FREEDM-84A672 PM7385 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots PM7385 within each independently timed T1/J1 or E1 link. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within a T1/J1 or E1 link. Unchannelised DS-3 links are assigned to a single HDLC channel.

Additionally, links of PM7385 may be configured independently to operate in an unframed or "clear channel" mode, in which the bit periods which are normally reserved for framing information in fact carry HDLC data. In unframed mode, links operate as unchannelised (i.e. the entire link is assigned to a single HDLC channel) regardless of link rate.

The FREEDM-84A672 supports mixing of channelised T1/J1/E1 and unchannelised or unframed links. The total number of channels of PM7385 in each direction is limited to 672. The maximum possible data rate over all links is 134.208 Mbps (which occurs with three DS-3 links running in unframed mode).

The FREEDM-84A672 supports three independently timed bidirectional clock/ data links, each carrying a single unchannellised HDLC stream. The links can be of arbitrary frame format and can operate at up to 51.84 MHz provided SYSCLK PM7385 is running at 45 MHz. When activated, each link replaces one of the SPEs conveyed on the SBI interface. (The maximum possible data rate when all three clock/data links are activated is 155.52 Mbps.)

The FREEDM-84A672 provides a low latency "Any-PHY" packet interface (APPI) to allow an external controller direct access into the 32 Kbyte partial packet buffers. Up to seven FREEDM-84A672 devices may share a single APPI. For each of the transmit of PM7385and receive APPI, the external controller is the master of the FREEDM-84A672 device sharing the APPI from the point of view of device selection. The external controller of PM7385 is also the master for channel selection in the transmit direction. In the receive direction, however, each FREEDM-84A672 device retains control over selection of its respective channels. The transmit of PM7385 and receive APPI is made up of three groups of functional signals polling, selection and data transfer. The polling signals are used by the external controller to interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.

The selection signals of PM7385 are used by the external controller to select a FREEDM- 84A672 device, or a channel within a FREEDM-84A672 device, for data transfer. The data transfer signals provide a means of transferring data across the APPI between the external controller and a FREEDM-84A672 device.

In the receive direction, polling and selection of PM7385 are done at the device level. Polling is not decoupled from selection, as the receive address pins serve as both a device poll address and to select a FREEDM-84A672 device. In response to a positive poll, the external controller of PM7385 may select that FREEDM-84A672 device for data transfer. Once selected, the FREEDM-84A672 prepends an in-band
channel address to each partial packet transfer across the receive APPI to associate the data with a channel. A FREEDM-84A672 must not be selected after a negative poll response.

In the transmit direction of PM7385, polling is done at the channel level. Polling is completely decoupled from selection. To increase the polling bandwidth, up to two channels may be polled simultaneously. The polling engine of PM7385 in the external controller runs independently of other activity on the transmit APPI. In response to a positive poll, the external controller may commence partial packet data transfer across the transmit APPI for the successfully polled channel of a FREEDM-84A672 device. The external controller must prepend an in-band channel address to each partial packet transfer across the transmit APPI to associate the data with a channel.

In the receive direction, the FREEDM-84A672 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-84A672 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as sharing of zeros between flags are supported. The resulting packet data is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. An external controller transfers partial packets out of the RAM, across the receive APPI bus, into host packet memory. The FREEDM-84A672 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum lengths. Receive APPI bus latency may cause one or more channels to overflow, in which case, the packets are aborted. The FREEDM-84A672 reports the status of each packet on the receive APPI at the end of each packet transfer.

Alternatively, in the receive direction, the FREEDM-84A672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-84A672 directly transfers the received octets onto the receive APPI verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots.

In the transmit direction, an external controller provides packets to transmit using the transmit APPI. For each provisioned HDLC channel, an external controller transfers partial packets, across the transmit APPI, into the internal 32 Kbyte transmit partial packet buffer. The partial packets are read out of the partial packet buffer by the FREEDM-84A672 and a frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag or idle sequence is automatically inserted when there is no packet data for a particular channel.

Sequential packets are optionally separated by a single flag (combined opening and closing flag) or up to 128 flags. Zeros between flags are not shared in the transmit direction although, as stated previously, they are accepted in the receive direction. Transmit APPI bus latency may cause one or more channels to underflow, in which case, the packets are aborted. The FREEDM-84A672 generates an interrupt to notify the host of aborted packets. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced on the transmit APPI. The FREEDM-84A672 will not attempt to re-transmit aborted packets.

Alternatively, in the transmit direction, the FREEDM-84A672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-84A672 directly inserts the transmitted octets provided on the transmit APPI. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive transmit APPI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-84A672 receives new data on the transmit APPI.

The FREEDM-84A672 is configured, controlled and monitored using the microprocessor interface. The FREEDM-84A672 is implemented in low power 2.5 Volt 0.25 m CMOS technology. All FREEDM-84A672 I/O are 3.3 volt tolerant. The FREEDM-84A672 is packaged in a 352 pin enhanced ball grid array (SBGA) package.