PM7382-PI

The PM7382-PI is designed as one kind of frame engine and datalink manager device that constants bit rate (CBR) data streams and each data stream (timeslot) carries an 8-bit byte of HDLC traffic, as described in the following section, and is characterised by 8 KHz framing. This device may be configured to support H-MVIP and may be configured to interface with H-MVIP digital telephony buses at 2.048 Mbps.

Features of the PM7382-PI are:(1)Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral Component Interconnect (PCI) Revision 2.1 bus for configuration;(2)Supports up to 256 bi-directional HDLC channels;(3)Supports up to 32 bi-directional HDLC channels;(4)Supports three bi-directional HDLC channels;(5)Links configured for channelised T1/J1/E1 or unchannelised operation;(6)For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation..

The absolute maximum ratings of the PM7382-PI can be summarized as:(1)Case Temperature under Bias: -40°C to +85°C;(2)Storage Temperature: -40°C to +125°C;(3)Supply Voltage (+3.3 Volt VDD3.3): -0.3V to +4.6V;(4)Supply Voltage (+2.5 Volt VDD2.5): -0.3V to +3.5V;(5)Voltage on Any non-PCI Pin: -0.3V to +6.0V;(6)Voltage on Any PCI Pin: -0.5V to VDD3.3 + 0.5V;(7)Static Discharge Voltage: ±1000 V;(8)Latch-Up Current: ±100 mA;(9)DC Input Current: ±20 mA;(10)Lead Temperature: +230°C;(11)Absolute Maximum Junction Temperature: +150°C. If you want to know more information such as the electrical characteristics about it, please download the datasheet in www.seekic.com or www.chinaicmart.com.

The PM7382-PI Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 256 bi-directional channels.

The PM7382-PI may be configured to support H-MVIP, channelised T1/J1/E1 or unchannelised traffic across 32 physical links.The PM7382-PI may be configured to interface with H-MVIP digital telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the PM7382-PI allows up to 256 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 2.048 Mbps H-MVIP operation, the PM7382-PI partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7,8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups.Links in each logical group share a common clock and a common type 0 frame pulse in each direction.

The PM7382-PI may be configured to interface with H-MVIP digital telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the PM7382-PI allows up to 256 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 8 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 8.192 Mbps H-MVIP operation, the PM7382-PI partitions the 32 physical links into 8 logical groups of 4 links. Only the first link, which must be located at physical links numbered 4m (0m7), of each logical group can be configured for 8.192 Mbps operation. The remaining 3 physical links in the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused. All links configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame pulse, a common frame pulse clock and a common data clock.