PM7381

`Single-chip multi-channel HDLC controller with a 50 MHz, 16 bit "Any-PHY" Packet Interface (APPI) for transfer of packet data using an external controller.
`Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are grouped into 4 logical groups of 8 links. A common clock and a type 0 frame pulse is shared among links in each logical group. The number of time-slots assigned to an HDLC channel is programmable from 1 to 32.
`Supports up to 672 bi-directional HDLC channels assigned to a maximum of 8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a common clock and a type 0 frame pulse. The number of time-slots assigned to an HDLC channel is programmable from 1 to 128.
`Supports up to 672 bi-directional HDLC channels assigned to a maximum of 32 channelised T1/J1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for E1).
`Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link, subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a clock rate of up to 10 MHz.
`Supports three bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running at 45 MHz.
`Supports a mix of up to 32 channelised, unchannelised and H-MVIP links, subject to the constraint of a maximum of 672 channels and a maximum aggregate link clock rate of 64 MHz in each direction.
`Links configured for channelised T1/J1/E1 or unchannelised operation support the gapped-clock method for determining time-slots which is backwards compatible with the FREEDM-8 and FREEDM-32 devices.
`For each channel, the HDLC receiver supports programmable flag sequence detection, bit de-stuffing and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
`For each channel, the receiver checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length. The receiver supports filtering of packets that are larger than a user specified maximum value.
`Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently on the receive APPI. For channelised links, the octets are aligned with the receive time-slots.
`For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
`For each channel, the HDLC transmitter supports programmable flag sequence generation, bit stuffing and frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the external controller or automatically when the channel underflows.
`Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from the transmit APPI. For channelised links, the octets are aligned with the transmit time slots.
`Supports per-channel configurable APPI burst sizes of up to 256 bytes for transfers of packet data.
`Provides 32 Kbytes of on-chip memory for partial packet buffering in both the transmit and the receive directions. This memory may be configured to support a variety of different channel configurations from a single channel with 32 Kbytes of buffering to 672 channels, each with a minimum of 48 bytes of buffering.
`Provides a 16 bit microprocessor interface for configuration and status monitoring.
`Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
`Supports 5 Volt tolerant I/O (except APPI).
`Low power 2.5 Volt 0.25 m CMOS technology.
`329 pin plastic ball grid array (PBGA) package.

The PM7381 FREEDM-32A672 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing for a maximum of 672 bi-directional channels. The FREEDM-32A672 may be configured to support H-MVIP, channelised T1/J1/E1 or unchannelised traffic across 32 physical links.

The FREEDM-32A672 may be configured to interface with H-MVIP digital telephony buses at 2.048 Mbps. For 2.048 Mbps H-MVIP links, the FREEDM- 32A672 allows up to 672 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 32 concatenated time-slots for each 2.048 Mbps H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link.

When configured for 2.048 Mbps H-MVIP operation, the FREEDM-32A672 partitions the 32 physical links into 4 logical groups of 8 links. Links 0 through 7, 8 through 15, 16 through 23 and 24 through 31 make up the 4 logical groups. Links in each logical group share a common clock and a common type 0 frame pulse in each direction.

The FREEDM-32A672 may be configured to interface with H-MVIP digital telephony buses at 8.192 Mbps. For 8.192 Mbps H-MVIP links, the FREEDM- 32A672 allows up to 672 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 8 H-MVIP links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 128 concatenated time-slots for each 8.192 H-MVIP link. Time-slots assigned to any particular channel need not be contiguous within the H-MVIP link. When configured for 8.192 Mbps H-MVIP operation, the FREEDM-32A672 partitions the 32 physical links into 8 logical groups of 4 links. Only the first link, which must be located at physical links numbered 4m (0m7), of each logical group can be configured for 8.192 Mbps operation. The remaining 3 physical links in the logical group (numbered 4m+1, 4m+2 and 4m+3) are unused.

All links configured for 8.192 Mbps H-MVIP operation will share a common type 0 frame pulse, a common frame pulse clock and a common data clock. For channelised T1/J1/E1 links, the FREEDM-32A672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1/J1 or E1 links. The gapped clock method to determine time-slot positions as per the FREEDM-8 and FREEDM-32 devices is retained. The channel assignment supports the concatenation of timeslots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1/J1 or E1 link. For unchannelised links, the FREEDM-32A672 processes up to 32 bi-directional HDLC channels within 32 independently timed links.

The links can be of arbitrary frame format. When limited to three unchannelised links, each link can be rated at up to 51.84 MHz provided SYSCLK is running at 45 MHz. For lower rate unchannelised links, the FREEDM-32A672 processes up to 32 links each rated at up to 10 MHz. In this case, the aggregate clock rate of all the links is limited to 64 MHz. The FREEDM-32A672 supports mixing of up to 32 channelised T1/J1/E1, unchannelised and H-MVIP links. The total number of channels in each direction is limited to 672.

The aggregate instantaneous clock rate over all 32 possible links is limited to 64 MHz. The FREEDM-32A672 provides a low latency "Any-PHY" packet interface (APPI) to allow an external controller direct access into the 32 Kbyte partial packet buffers. Up to seven FREEDM-32A672 devices may share a single APPI. For each of the transmit and receive APPI, the external controller is the master of each FREEDM-32A672 device sharing the APPI from the point of view of device selection. The external controller is also the master for channel selection in the transmit direction. In the receive direction, however, each FREEDM-32A672 device retains control over selection of its respective channels. The transmit and receive APPI is made up of three groups of functional signals polling, selection and data transfer. The polling signals are used by the external controller to interrogate the status of the transmit and receive 32 Kbyte partial packet buffers.

The selection signals are used by the external controller to select a FREEDM- 32A672 device, or a channel within a FREEDM-32A672 device, for data transfer. The data transfer signals provide a means of transferring data across the APPI between the external controller and a FREEDM-32A672 device. In the receive direction, polling and selection are done at the device level. Polling is not decoupled from selection, as the receive address pins serve as both a device poll address and to select a FREEDM-32A672 device. In response to a positive poll, the external controller may select that FREEDM-32A672 device for data transfer. Once selected, the FREEDM-32A672 prepends an in-band channel address to each partial packet transfer across the receive APPI to associate the data with a channel.

A FREEDM-32A672 must not be selected after a negative poll response. In the transmit direction, polling is done at the channel level. Polling is completely decoupled from selection. To increase the polling bandwidth, up to two channels may be polled simultaneously. The polling engine in the external controller runs independently of other activity on the transmit APPI. In response to a positive poll, the external controller may commence partial packet data transfer across the transmit APPI for the successfully polled channel of a FREEDM-32A672 device.

The external controller must prepend an in-band channel address to each partial packet transfer across the transmit APPI to associate the data with a channel. In the receive direction, the FREEDM-32A672 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32A672 delineates the packet boundaries using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as sharing of zeros between flags are supported. The resulting packet data is placed into the internal 32 Kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. An external controller transfers partial packets out of the RAM, across the receive APPI bus, into host packet memory.

The FREEDM-32A672 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum lengths. Receive APPI bus latency may cause one or more channels to overflow, in which case, the packets are aborted.

The FREEDM-32A672 reports the status of each packet on the receive APPI at the end of each packet transfer. Alternatively, in the receive direction, the FREEDM-32A672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32A672 directly transfers the received octets onto the receive APPI verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots. In the transmit direction, an external controller provides packets to transmit using the transmit APPI.

For each provisioned HDLC channel, an external controller transfers partial packets, across the transmit APPI, into the internal 32 Kbyte transmit partial packet buffer. The partial packets are read out of the partial packet buffer by the FREEDM-32A672 and a frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link. The flag or idle sequence is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by a single flag (combined opening and closing flag) or up to 128 flags. Zeros between flags are not shared in the transmit direction although, as stated previously, they are accepted in the receive direction. Transmit APPI bus latency may cause one or more channels to underflow, in which case, the packets are aborted.

The FREEDM-32A672 generates an interrupt to notify the host of aborted packets. For normal traffic, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced on the transmit APPI.

The FREEDM-32A672 will not attempt to re-transmit aborted packets. Alternatively, in the transmit direction, the FREEDM-32A672 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32A672 directly inserts the transmitted octets provided on the transmit APPI. If the transparent channel is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows due to excessive transmit APPI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes immediately when the FREEDM-32A672 receives new data on transmit APPI.

The FREEDM-32A672 is configured, controlled and monitored using the microprocessor interface. The FREEDM-32A672 is implemented in low power 2.5 Volt 0.25 m CMOS technology. All FREEDM-32A672 I/O except those belonging to the APPI are 5 volt tolerant. The APPI I/O are 3.3 volt tolerant. The FREEDM-32A672 is packaged in a 329 pin plastic ball grid array (PBGA) package.