PM7367-PI

DescriptionThe PM7367-PI is a kind of Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller. It is available in 272 Plastic Ball Grid Array (PBGA) package.It is widely used in DCC processing in SONET/SDH interfaces and packet-based DSLAM equipment. There are some f...

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SeekIC No. : 004463787 Detail

PM7367-PI: DescriptionThe PM7367-PI is a kind of Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller. It is available in 272 Plastic Ball Grid Array (PBGA) package.It is widel...

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Part Number:
PM7367-PI
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Description

The PM7367-PI is a kind of Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller. It is available in 272 Plastic Ball Grid Array (PBGA) package.It is widely used in DCC processing in SONET/SDH interfaces and packet-based DSLAM equipment.

There are some features ofPM7367-PI as follows: (1)Supports up to 32 bi-directional HDLC channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1); (2)Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can; (3)have a clock rate of up to 10 MHz; (4)Supports up to two bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz; (5)Supports a mix of up to 32 channelised and unchannelised links; subject to the constraint of a maximum of 32 channels and a maximum aggregate link clock rate of 64 MHz in each direction; (6)Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots; (7)For each channel, time-slots are selectable to be in 56 kbits/s format or 64kbits/s clear channel format; (8)Supports PCI burst sizes of up to 128 bytes for transfers of packet data; (9)Pin compatible with PM7366-PI (FREEDM-8 PBGA) device.; (10)Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes; (11)Supports 3.3 and 5 Volt PCI signaling environments.

Then is about the absolute maximum ratings of PM7367-PI: (1)Case Temperature under Bias: -40 to +85; (2)Storage Temperature: -40°C to +125°C; (3)Supply Voltage (VDD): -0.3V to +4.6V; (4)Bias Voltage (VBIAS): (VDD - 0.3) to +5.5V; (5)Voltage on Any Pin: -0.3V to VBIAS + 0.3V; (6)Static Discharge Voltage: ±1000 V; (7)Latch-Up Current: ±100 mA; (8)DC Input Current: ±20 mA; (9)Lead Temperature: +230; (10)Absolute Maximum Junction Temperature: +150.




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