PM7364

·Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel HDLC controller.
·Supports up to 128 bi-directional HDLC channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1).
·Supports up to 32 bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link; subject to a maximum aggregate link clock rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can have a clock rate of up to 10 MHz.
·Supports up to two bi-directional HDLC channels each assigned to an unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz.
·Supports a mix of up to 32 channelised and unchannelised links; subject to the constraint of a maximum of 128 channels and a maximum aggregate link clock rate of 64 MHz in each direction.
·For each channel, the HDLC receiver performs flag sequence detection, bit de-stuffing, and frame check sequence validation. The receiver supports the validation of both CRC-CCITT and CRC-32 frame check sequences. The receiver also checks for packet abort sequences, octet aligned packet length and for minimum and maximum packet length.
·Alternatively, for each channel, the receiver supports a transparent mode where each octet is transferred transparently to host memory. For channelised links, the octets are aligned with the receive time-slots.
·For each channel, time-slots are selectable to be in 56 kbits/s format or 64 kbits/s clear channel format.
·For each channel, the HDLC transmitter performs flag sequence generation, bit stuffing, and, optionally, frame check sequence generation. The transmitter supports the generation of both CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows.
·Supports two levels of non-preemptive packet priority on each transmit channel. Low priority packets will not begin transmission until all high priority packets are transmitted.
·Alternatively, for each channel, the transmitter supports a transparent mode where each octet is inserted transparently from host memory. For channelised links, the octets are aligned with the transmit time-slots.
·Directly supports a 32-bit, 33 MHz PCI 2.1 interface for configuration, monitoring and transfer of packet data, with an on-chip DMA controller with scatter/gather capabilities.
·Provides 8 kbytes of on-chip memory for partial packet buffering in each direction. This memory can be configured to support a variety of different channel configurations from a single channel with 8 kbytes of buffering to 128 channels, each with a minimum of 48 bytes of buffering.
·Supports PCI burst sizes of up to 128 bytes for transfers of packet data.
·Pin compatible with PM7366 (FREEDM-8) device.
·Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
·Supports 3.3 and 5 Volt PCI signaling environments.
·Low power CMOS technology.
·256 pin enhanced ball grid array (SBGA) package (27 mm X 27 mm).

The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels. For channelised links, the FREEDM-32 allows up to 128 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed T1 or E1 links. The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated timeslots for a T1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within the T1 or E1 link.

For unchannelised links, the FREEDM-32 processes up to 32 bi-directional HDLC channels within 32 independently timed links. The links of PM7364 can be of arbitrary frame format. When limited to two unchannelised links, each link can be rated at up to 45 MHz when SYSCLK is at 25 MHz and at up to 52 MHz when SYSCLK is at 33 MHz. For lower rate unchannelised links, the FREEDM-32 processes up to 32 links, where the aggregate clock rate of all the links is limited to 64 MHz, links 0 to 2 can have a clock rate of up to 45 MHz when SYSCLK PM7364 is at or above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz and links 3 to 31 can have a clock rate of up to 10 MHz.

The FREEDM-32 supports mixing of up to 32 channelised and unchannelised links. The total number of channels in each direction is limited to 128. The aggregate clock rate over all 32 possible links is limited to 64 MHz.

In the receive direction, the FREEDM-32 performs channel assignment and packet extraction and validation. For each provisioned HDLC channel, the FREEDM-32 delineates the packet boundaries of PM7364 using flag sequence detection, and performs bit de-stuffing. Sharing of opening and closing flags, as well as, sharing of zeros between flags are supported. The resulting packet data of PM7364 is placed into the internal 8 kbyte partial packet buffer RAM. The partial packet buffer acts as a logical FIFO for each of the assigned channels. Partial packets are DMA'd out of the RAM, across the PCI bus and into host packet memory.

The FREEDM-32 validates the frame check sequence for each packet, and verifies that the packet is an integral number of octets in length and is within a programmable minimum and maximum length. The receive packet status of PM7364 is updated before linking the packet into a receive ready queue. The FREEDM-32 alerts the PCI Host that there are packets in a receive ready queue by, optionally, asserting an interrupt on the PCI bus.

Alternatively, in the receive direction, the FREEDM-32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32 directly transfers the received octets into host memory verbatim. If the transparent channel is assigned to a channelised link, then the octets are aligned to the received time-slots.

In the transmit direction, the PCI Host provides packets to transmit using a transmit ready queue. For each provisioned HDLC channel, the FREEDM-32 DMA's partial packets across the PCI bus and into the transmit partial packet buffer. The partial packets are read out of the packet buffer by the FREEDM-32 and frame check sequence is optionally calculated and inserted at the end of each packet. Bit stuffing is performed before being assigned to a particular link.

The flag sequence of PM7364 is automatically inserted when there is no packet data for a particular channel. Sequential packets are optionally separated by two flags (an opening flag and a closing flag) or a single flag (combined opening and closing flag). Zeros between flags are not shared. PCI bus latency may cause one or more channels to underflow, in which case, the packets are aborted, and the host is notified. For normal traffic, an abort sequence of PM7364 is generated, followed by inter-frame time fill characters (flags or all-ones bytes) until a new packet is sourced from the PCI host. No attempt is made to automatically re-transmit an aborted packet.

Alternatively, in the transmit direction, the FREEDM-32 supports a transparent operating mode. For each provisioned transparent channel, the FREEDM-32 directly inserts the transmitted octets from host memory. If the transparent channel ofPM7364 is assigned to a channelised link, then the octets are aligned to the transmitted time-slots. If a channel underflows of PM7364 due to excessive PCI bus latency, an abort sequence is generated, followed by inter-frame time fill characters (flags or all-ones bytes) to indicate idle channel. Data resumes of PM7364 immediately when the FREEDM-32 receives new data from the host.

The FREEDM-32 is configured, controlled and monitored using the PCI bus interface. The FREEDM-32 is implemented in low power CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 256 pin enhanced ball grid array (SBGA) package.