PM7351

• Integrated analog/digital device that interfaces a high speed parallel bus to 8 bidirectional data streams.
• Each stream travels over a high speed nLow Voltage Differential Signal (LVDS) serial link.
• Interfaces to 8 S/UNI®-DUPLEX devices (via the LVDS links) to create a point-to-multipoint serial backplane architecture.
• In the LVDS receive direction: accepts cell streams from the 8 LVDS links, multiplexing them into a single cell stream, which is presented to the system bus as a single UTOPIA L2 compatible PHY.
• In the LVDS transmit direction: receives cell streams from the bus master, and routes the cells to the appropriate serial link.
• Cell read/write to the 8 LVDS links is available via the microprocessor port.
• Provides optional hardware assisted CRC32 calculation across cells, which creates an embedded inter-processor communication channel across the LVDS links.
• Optionally routes the embedded control channels from the 8 links to/ from the system bus.
• Under software control, the 8 LVDS links can be individually marked active or standby. This is used by the far end S/UNI-DUPLEX to implement 1:1 protected systems.
• Error monitoring and cell counting on all links.
• Requires no external memories.
• Low power 3.3V CMOS technology.
• Standard 5 pin P1149 JTAG port.
• 304 ball SBGA, 31mm x 31mm.