PM7350

• Integrated analog/digital device that interfaces a high-speed parallel bus to a high speed Low Voltage Differential Signal (LVDS) serial link with optional 1:1
protection.
• For framers or modems without Utopia bus interfaces the S/UNI-DUPLEX provides cell delineation (I.432) across 16 clock and data (bit serial) interfaces.
• Fault detection, redundancy, protection switching, and inserting/removing cards while the system is running (hot swap).
• Interface to other S/UNI-DUPLEX or S/UNI-VORTEX, to satisfy a full set of system level requirements for backplane interconnect:
• Transports user data by providing the inter-card data-path.
• Inter-processor communication by providing an integrated inter-card control channel.
• Exchanges flow control information (back-pressure) to prevent data loss.
• Provides embedded command and control signals across the backplane: system reset, error indications, protection switching commands, etc.
• Clock/timing distribution (system clocks as well as reference clocks such as 8 kHz timing references).
• When used as a parallel bus slave device, can be configured to share the bus with other S/UNI-DUPLEX bus slave devices.
• Can interface to another S/UNI-DUPLEX device (via a single LVDS link) to create a simple point-to-point "Utopia bus extension" capability.
• Can interface to two S/UNI-DUPLEX devices to create a 1:1 protected bus extension.
• Interworks with PM7351 S/UNI-VORTEX devices to implement a point-tomultipoint serial backplane architecture, with optional 1:1 protection of the common  card.
• In the LVDS receive direction: selects traffic from the LVDS link marked active and demultiplexes the individual cell streams to the appropriate PHY device.

The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit typically used with its sister device, the S/UNI-VORTEX, to implement a point-to-point serial backplane interconnect architecture. The primary role of PM7350 of the S/UNI-DUPLEX is to interface to up to 32 devices (typically framers or PHYs) and transfer 52-56 byte data cells in serial format to/from a backplane. Devices interface to the S/UNI-DUPLEX via an 8 or 16-bit SCI-PHY/Utopia/Any-PHY bus, or optionally via a 16 port clock and data interface.

Each S/UNI-DUPLEX PM7350 can connect to two 100 to 200 Mb/s Low Voltage Differential Signal (LVDS) serial links. A microprocessor port provides acce ss to internal configuration and monitoring registers. The microprocessor port may also be used to insert and extract cells in support of an embedded microprocessor communication channel.