PM7349

• Quad DS-3, E3 (G.751 and G.832), and J2 framers.
• Each channel can be independently configured to be a DS-3, E3, or J2 Framer.
• Gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits.
• Provides programmable pseudorandom test pattern generation, detection, and analysis features.
• Provides integral transmit and receive HDLC controllers with 128-byte FIFO  depths.
• Provides performance monitoring counters suitable for accumulation periods of up to 1 second.
• Provides an 8-bit microprocessor interface for configuration, control and status monitoring.
• Provides a standard five signal P1149.1 JTAG test port for boundaryscan board test purposes.
• Low power 3.3 V CMOS technology with 5 V tolerant inputs.
• Available in a high density 256-pin SBGA package (27 mm x 27 mm).