PM7346

Features: · Single chip quad ATM User Network Interface operating at 44.736 Mbit/s, 4.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-94- 406R5, and AF-PHY-0029.000. Each line can be individually configured for he desired rate.· Implements ATM Direct Cell Mapping into DS1, DS3, E1,...

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SeekIC No. : 004463775 Detail

PM7346: Features: · Single chip quad ATM User Network Interface operating at 44.736 Mbit/s, 4.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-94- 406R5, and AF-PHY-0029.000. Each line can be...

floor Price/Ceiling Price

Part Number:
PM7346
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

· Single chip quad ATM User Network Interface operating at 44.736 Mbit/s, 4.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-94- 406R5, and AF-PHY-0029.000. Each line can be individually configured for he desired rate.
· Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2 ransmission systems according to ITU-T Recommendation G.804.  Provides a UTOPIA Level 2 compatible ATM-PHY Interface.
· Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and S3 transmission systems according to the ATM Forum User Network nterface Specification and ANSI TA-TSY-000773, TA-TSY-000772, and E1 nd E3 transmission systems according to the ETSI 300-269 and ETSI 300- 70.
· Support is provided for SMDS and ATM mappings into various rate ransmission systems as follows:

 




Application

· Provides programmable pseudo-random test pattern generation, detection, nd analysis features.
· Provides integral transmit and receive HDLC controllers with 128-byte FIFO epths.
· Provides performance monitoring counters suitable for accumulation periods f up to 1 second.
· Provides an 8-bit microprocessor interface for configuration, control and tatus monitoring.
· Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board est purposes.
· Low power 3.3V CMOS technology with 5V tolerant inputs.
· Available in a high density 256-pin SBGA package (27mm x 27mm).



Description

The PM7346 S/UNI-QJET is a quad ATM physical layer processor with integrated S3, E3, and J2 framers. PLCP sublayer DS1, DS3, E1, and E3 processing is upported as is ATM cell delineation.

The S/UNI-QJET contains integral DS3 framers, which provide DS3 framing and rror accumulation in accordance with ANSI T1.107, and T1.107a, integral E3 ramers, which provide E3 framing in accordance with ITU-T Recommendations .832 and G.751, and integral J2 framers, which provide J2 framing in ccordance with ITU-T Recommendation G.704 and I.432.

When configured for DS3 transmission system of PM7346 sublayer processing, the /UNI-QJET accepts and outputs both digital B3ZS-encoded bipolar and nipolar signals compatible with M23 and C-bit parity applications.

When configured for E3 transmission system of PM7346 sublayer processing, the /UNI-QJET accepts and outputs both HDB3-encoded bipolar and unipolar ignals compatible with G.751 and G.832 applications.

When configured for J2 transmission system of PM7346 sublayer processing, the /UNI-QJET accepts and outputs both B8ZS-encoded bipolar and unipolar ignals compliant with G.704 and NTT 6.312 Mbit/s applications.

When configured for DS1, or E1 transmission system of PM7346 sublayer processing, the /UNI-QJET accepts and outputs unipolar signals with appropriate clock and rame pulse signals for physical sublayer processing. When configured for other ransmission systems, the S/UNI-QJET provides a generic interface for physical ublayer processing.

In the DS3 receive direction, the S/UNI-QJET frames of PM7346 to DS3 signals with a aximum average reframe time of 1.5 ms and detects line code violations, loss f signal, framing bit errors, parity errors, path parity errors, AIS, far end receive ailure and idle code. The DS3 overhead bits are extracted and presented on erial outputs. When in C-bit parity mode, the Path Maintenance Data Link and he Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers re provided for Path Maintenance Data Link support. In addition, valid bitoriented odes in the FEAC channels are detected and are available through the icroprocessor port.

In the E3 receive direction, the S/UNI-QJET frames to G.751 and G.832 E3 ignals with a maximum average reframe times of 135s for G.751 frames and 50s for G.832 frames. Line code violations, loss of signal, framing bit errors,




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