PM7329

• Monolithic single chip ATM traffic manager providing VC queuing/shaping and VC, Class Of Service(COS), and Port scheduling, congestion management, and switching across 128 ports.
• Targeted at systems where many low speed ATM data ports are multiplexed onto few high speed ports.
• 869 Kcells/s non shaped throughput in full duplex.
• 1.73 Mcells/s non shaped throughput in half duplex.
• 1.42 Mcells/s shaped throughput (aggregate of the four shapers).
• Supports four WAN uplink ports, with port aliasing.
• Supports 128 loop ports. Loop port can support an uncongested rate up to 230Kcells/sec.
• Provides 4 Classes of Service per port with configurable traffic parameters enabling support for a mix of CBR, VBR, GFR, and UBR classes.
• Provides 1024 per-VC queues individually assignable to any COS in any port.
• Provides support of up to 256k cells of shared buffer.
• Provides 2 independent cell emission schedulers, 1 for the WAN ports, and 1 for the Loop ports. The schedulers have the following features: Three level hierarchical cell emission scheduling at the port, class, and VC levels.
• WAN Port Scheduling:
• Weighted Interleaved Round Robin WAN port scheduling.
• Per port Priority Fair Queued class scheduling with port independence.
• Per Class:
• Weighted Fair Queued VC scheduling with class independence or,
• Shaped Fair Queued VC scheduling applying rate based per VC shaping or,
• Frame Continuous Queued VC scheduling for VC Merge and packet re-assembly.
• Loop Port Scheduling:
• Weighted Interleaved Round Robin Loop port scheduling.
• Per port Priority Fair Queued class scheduling with port independence.
• Per Class:
• Weighted Fair Queued VC scheduling with class independence or,
• Frame Continuous Queued scheduling for VC Merge and packet re-assembly.
• Congestion Control applied per-VC, per-class, per-port and per-direction.
• Flexible, progressive hierarchical throttling of buffer consumption. Provides sharing of resources during low congestion, memory reservation during high congestion.
• Applies EPD and PPD on a per-VC, per-class, per-port, and per-direction basis with CLP differentiation, following emerging GFR standards.
• Provides EFCI marking on a per VC basis.
• Provides interrupts and indication of most recent VC/Class/Port that exceeded maximum thresholds.
• Provides flexible VPC or VCC switching selectable on a per VC basis as follows:
• Any WAN port to any WAN port.
• Any WAN port to any Loop port.
• Any Loop port to any WAN port.
• Any Loop port to any Loop port.
• Microprocessor port to any loop or WAN port.
• Any loop or WAN port to microprocessor port.
• VP Termination (in conjunction with the S/UNI-ATLAS).
• VPI or VPI/VCI header mapping.
• VC merge.
• Provides flexible signaling and control capabilities:
• Provides 4 independent uP transmit queues.
• Provides simultaneous AAL5 SAR assistance for traffic to/from the uP on up to 1024 VCs.
• Supports uP cell injection into any queue.
• Provides per VC selectable OAM cell pass through or switching to microprocessor port.
• Supports CRC10 calculation for OAM cells destined for/originating from the microprocessor.
• Diagnostic access provided to context memory and cell buffer memory via the microprocessor.
• Provides per VC CLP0/1 transmit counts.
• Provide global per CLP0/1 discard counts.
• Provides various error statistics accumulation.
• Determines the ingress connection identifier from one of several locations: the cell prepend, the VPI/VCI field, or the HEC/UDF field.
• Interface support:
• Provides a 8/16-bit Any-PHY compliant master/slave Loop side interface supporting up to 128 ports (logical PHYs).
• Provides an 8/16-bit Any-PHY compliant master/slave WAN side interface supporting up to 4 ports (PHYs).
• Provides a 32-bit multiplexed microprocessor bus interface for signaling, control, and cell message extraction and insertion, context memory access, control and status monitoring, and configuration of the IC.
• Provides a 32-bit SDRAM interface for cell buffering.
• Provides a 36-bit pipelined ZBT or register to register late write SSRAM interface for context storage.
• Packaging:
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
• Implemented in low power, 0.25 micron, +2.5/3.3V CMOS technology with CMOS compatible inputs and outputs.
• 352-pin high-performance ball grid array (SBGA) package.

The PM7329 S/UNI-APEX-1K800 is a full duplex ATM traffic management device, providing cell switching, per VC queuing, traffic shaping, congestion management, and hierarchical scheduling to up to 128 loop ports and up to 4 WAN ports.

The S/UNI-APEX-1K800 provides per-VC queuing for 1024 VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS.