PM7322

• Monolithic single-chip device which handles ATM switch ingress VPI/VCI address translation, cell appending, cell rate policing, counting, and OAM requirements for 65,536 Virtual Circuits (VCs).
• Instantaneous transfer rate of 800 Mbit/s supports a cell transfer rate of 1.42 x 10⁶ cells/s.
• 8- or16-bit PHY interface using direct addressing for up to four PHYs (UTOPIA Level 1) and Multi-PHY addressing for up to 32 PHYs (UTOPIA Level 2).
• 8- or 16-bit SCI-PHYä+ (53 -64 byte extended ATM cell with prepend/ postpend) interface at output to switch fabric.
• Compatible with wide range of switching fabrics and traffic management architectures including per-VC or per-PHY queuing.
• Provides identification/tagging of RM cells to support adjunct processing applications such as Virtual Source/ Virtual Destination (VS/VD) Available Bit Rate (ABR) service.
• Supports logical multicast.
• Extremely flexible CAM-type cell dentification that uses arbitrary VPI/ VCI values and/or appended bytes for identification.
• Drops on command all low priority (CLP=1) cells to relieve switch congestion.
• Includes 16-bit FIFO buffered microprocessor bus interface for cell extraction and insertion (including OAM), VC table access, control and status monitoring, and configuration of the IC.
• Supports DMA access for cell extraction and insertion.
• Low power, 0.6 micron, +5 V CMOS technology.
• 240 copper slugged Plastic Quad Flat Pack (PQFP) package.
• Policing done according to the Virtual Scheduling Algorithm (equivalent to Continuous-State Leaky Bucket Algorithm).
• Two instantiations of policing per VC.