Features: nterface Features• Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one45 Mbit/s or less data stream.• Supports 256 Virtual Channels (VCs) (32 per line).• Supports n ´ 64 structured data format.• Supports arbitrary timeslot-to-VC m...
PM73121: Features: nterface Features• Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one45 Mbit/s or less data stream.• Supports 256 Virtual Channels (VCs) (32 per li...
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nterface Features
• Provides AAL1 segmentation and reassembly of eight 2 Mbit/s data streams or one
45 Mbit/s or less data stream.
• Supports 256 Virtual Channels (VCs) (32 per line).
• Supports n ´ 64 structured data format.
• Supports arbitrary timeslot-to-VC mappings, including alternating timeslots.
• Provides Common Channel Signaling (CCS) and Channel Associated Signaling (CAS)
configuration options.
• Provides per-VC data and signaling conditioning in both the transmit and the receive irections.
• Arbitrates a 16-bit microprocessor interface to a 128K ´ 16 (12 ns) SRAM.
• Supports multicast connections, ATM Monitoring (AMON), Remote Monitoring RMON), and ATM Circuit Steering (ACS).
• Supports adaptive clocking in Structured Data Format, Frame-based (SDF-FR), tructured Data Format, Multiframe-based (SDF-MF), and Unstructured Data Format, ultiple Line (UDF-ML) modes. ransmit Cell Interface Features
• Provides an ATM-layer or PHY-layer 33 MHz UTOPIA interface. Both Single PHY
(SPHY) and Multi-PHY (MPHY) modes are supported.
• Provides per-VC transmit queueing.
• Provides a calendar queue service algorithm that produces minimal Cell Delay Variation CDV).
• Provides a supervisory transmit buffer for Operations, Administration, and Maintenance OAM), and for ATM signaling.
• Generates pointers for structured data transmission.
• Provides sequence number and sequence number protection generation.
• Provides partially filled cell generation with the length configurable on a per-VC basis.
• Generates and transmits Synchronous Residual Time Stamp (SRTS) values for nstructured modes.
• Built-in transmit line clock generation based on received SRTS values, receive line clock, a nominal frequency.
The1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, 3, or DS3 PM73121 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate CBR) ATM network. PM73121 arbitrates access to an external SRAM for storage of the configuration, he user data ofPM73121, and the statistics. The device provides a microprocessor interface for configuration, anagement, and statistics gathering. PMC-Sierra also offers a software device control package or the AAL1gator II device.