PM5945-UTP5

UTOPIA Interface
The UTOPIA Interface makes the S/UNI drop side receive and transmit signals compatible with the UTOPIA 1.04 interface specification. PM5945-UTP5 consists of two high speed 22V10 PALs, two high speed IDT74FCT377C buffers, and a receive IDT72201 clocked FIFO. The 22V10 PALs can be replaced with faster versions if you must run at a higher than 20 MHz TxClk and RxClk clock signals.

The Transmit drop side interface of PM5945-UTP5 is controlled by the ATM layer through the edge connector. All the transmit signals from the ATM layer change with respect to the TxClk. All the input signals to the ATM layer are sampled on the rising edge of the TxClk.

The S/UNI device asserts the TCA signal when it has a complete empty cell available. This signal goes to the PAL (U17) and causes the TxFullB signal to the ATM layer to be de-asserted (high). The ATM layer PM5945-UTP5 asserts the TxClavB signal (low) when it has a complete Cell of data to transfer to the PHY device. The TxEnbB signal from the ATM layer (Vicksburg card) is the output of the TxFullB signal from the PHY layer gated with the TxClavB signal from the ATM layer. The way the TxEnbB signal goes active (low) depends on whether the ATM layer of PM5945-UTP5 is ready to send a cell of data before the PHY layer becomes available to accept the data, or whether the PHY layer is ready to accept a cell of data before the ATM layer is ready to send data.

The case where the ATM layer PM5945-UTP5 has a cell available for transmission before the PHY layer is ready to accept the cell is handled as follows; The Vicksburg card drives the TSOC signal active (high) and the TxData bus with valid octet byte zero coincident with the assertion of the TxClavB signal, and waits for the TxFullB signal from the PHY layer to go inactive (high). When the PHY device has a cell available, the TxFullB signal goes inactive (high) and then the TxEnbB signal is immediately asserted (low) (after a delay through a gate). On the next rising edge of the TxClk signal, the second byte of data of PM5945-UTP5 is driven onto the TxData bus and the TSOC signal is de-asserted (low).

The case where the PHY layer is ready to accept a cell of data before the ATM layer PM5945-UTP5 is ready to transmit the cell is handled as follows; The PHY layer de-asserts the TxFullB signal (high) and waits for the TxEnbB signal to go active (low). When the ATM layer has a cell available for transmission, the TxClavB is set active (low) on the rising edge of the TxClk signal, and drives the TSOC signal active (high)of PM5945-UTP5 and the TxData bus with valid octet byte zero . The TxClavB signal sets the TxEnbB signal active (low) through a gate delay.

In either case, the TxData bus PM5945-UTP5 is continually clocked into the first buffer (U18) by the rising edges of the TxClk signal. The assertion of the TxEnbB signal enables the TWRB signal ofPM5945-UTP5 to the S/UNI device. On the falling edge of the TWRB signal (rising edge of TxClk) the data from U18 is clocked into the second buffer (U19). The clock signal to U19 is generated by the PAL (inverted TxClk). The ATM layer updates the TxData with new data on the rising edge of each TxClk signal while TxEnbB is asserted and the TxFullB signal is de-asserted (high). If at the end of the current cell
transfer, another cell ofPM5945-UTP5 is available (TCA remains active), the TxFullB will still be asserted (low) on the 51'st byte transferred. This is to accomodate the propagation delay of TCA going inactive (low) at the end of a cell transfer and then being sampled by the PAL (TCA must be sampled as it can go active at any time). This will incur an extra clock delay per cell transfer. The TxClavB PM5945-UTP5 signal goes inactive (high) for a minimum of two cycles per cell trasfer. There will be a 3 clock cycle delay per cell transfer as the TxFullB and the TxClavB overlap.

The Receive drop side interface of PM5945-UTP5 is controlled by the ATM layer through the edge connector. All the receive signals from the ATM layer change with respect to the RxClk. All the input signals to the ATM layer are sampled on the rising edge of the RxClk. The receive side incorporates a external FIFO so that the S/UNI device does not overrun due to the latency times between burst cell reads of the ATM layer (Vicksburg mother board).

The S/UNI device asserts the RCA signal when PM5945-UTP5 has a complete cell to transfer to the FIFO. The RCA signal goes to the Receive PAL (U16) and the PAL asserts the write enables to the receive FIFO. If the receive FIFO is not full (/FF high), the receive PAL will start clocking the data from the S/UNI into the FIFO by generating the RRDB clock signal. The RSOC signal PM5945-UTP5 from the S/UNI is inserted into bit 9 of the FIFO data inputs. The FIFO enables the /FF (active low FIFO Full) signal when it is full which disables further transfer of data from the S/UNI to the FIFO. If the FIFO gets full, the S/UNI PM5945-UTP5 will have transferred an indeterminate portion of a cell. The rest of the cell will get transferred as soon as the FIFO de-activates the /FF signal. The Receive PAL uses the RxCLK signal from the ATM layer to generate the WClk signal going to the FIFO and the RRDB clock signal to the S/UNI. The WEN going to the FIFO is disabled while the /FF is active (low). While the FIFO write enable is disabled, the clock going to the FIFO is the same as the RxCLK. This is done because the FIFO /FF signal will not be disabled (high) untill it gets a rising edge on the WCLK input.

The RxEmptyB signal comes from the Receive FIFO /EF (active low Empty FIFO) signal. The Receive FIFO PM5945-UTP5 de-asserts the the RxEmptyB signal (high) upon reception of a single byte of data. On the next rising edge of the RxClk clock signal, the ATM layer samples the RxEmptyB signal and on the following RxClk clock signal, the ATM layer activates the RxEnbB signal (low) if it has an empty cell available. The RxEnbB PM5945-UTP5 signal from the ATM layer goes to the Receive PAL (U16) and to the read enable (/RDEN1) input of the receive FIFO PM5945-UTP5. On the next rising edge of the RxCLK signal after the RxEnbB signal goes active (low) the first byte of data is clocked out of the FIFO along with the RSOC signal. The receive ATM layer ignores the data until PM5945-UTP5 sees a valid RSOC signal. Once cell transfer has commenced, the ATM layer
expects a complete cell transfer. If the FIFO of PM5945-UTP5 is empty (RxEmptyB is active) and then the S/UNI starts to transfer data to the FIFO, there might only be one byte in the FIFO before the RxEmptyB signal could go inactive (high). For the FIFO to become empty, the S/UNI must not have had any cells to transfer and therefore the first byte in the FIFO would be the first byte of the Cell of PM5945-UTP5 along with the valid RSOC signal. Since the RxClk clock signal is generating the write and read clock signals to the FIFO as well as the read clock signal to the S/UNI, the ATM layer PM5945-UTP5 cannot read the data out of the FIFO faster than the S/UNI can write the data into the FIFO.