PM5381

1.1 General
• Single chip ATM and POS User-Network Interface operating at 2488.32 Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615(1619)/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).
• Processes bit-serial 2488.32 Mbit/s STS-48 (STM-16-16c) data streams with on-chip clock and data recovery and clock synthesis.
• Complies with Bellcore GR-253-CORE jitter tolerance, jitter transfer and intrinsic jitter criteria.
• Provides termination for SONET Section, Line and Path overhead or SDH Regenerator Section, Multiplexer Section and High Order Path overhead.
• Provides UTOPIA Level 3 32-bit wide System Interface (clocked up to 104 MHz) with parity support for ATM applications.
• Provides SATURN POS-PHY Level 3
32-bit System Interface (clocked up to 104 MHz) for Packet
over SONET (POS), or ATM applications.
• Supports line loopback from the line side receive stream to the transmit stream and diagnostic loopback from the line side transmit stream to the line side receive stream interface.
• Provides support for automatic protection switching via a 4-bit LVDS 777.76 MHz port.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 16-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 1.8V CMOS core logic with 3.3V CMOS/TTL compatible digital inputs and digital outputs. PECL inputs and outputs are 3.3V compatible.
• Industrial temperature range (-40C to +85C).
• 416 pin UBGA package.
1.2 SONET Section and Line / SDH Regenerator and Multiplexer Section
• Frames to the SONET/SDH receive stream and inserts the framing bytes (A1, A2) and the section trace byte (J0) into the transmit stream; descrambles the received stream and scrambles the transmit stream.
• Calculates and compares the bit interleaved parity (BIP) error detection codes (B1, B2) for the receive stream. Calculates and inserts B1 and B2 in the transmit stream. Accumulates near end errors (B1, B2) and far end errors (M1) and inserts line remote error indications (REI) into the M1 byte based on received B2 errors.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B1 errors.
• Extracted and optionally inserts on dedicated pins the SONET/SDH transport overhead for an STS- 48c/STM-16c frame.
• Extracts and serializes on dedicated pins the data communication channels (D1-D3, D4-D12) and inserts the corresponding signals into the transmit stream.
• Extracts and filters the automatic protection switch (APS) channel (K1, K2) bytes into internal registers. Inserts the APS channel into the transmit stream.
• Extracts and filters the synchronization status message (S1) byte into an internal register for the receive stream. Inserts the synchronization status message (S1) byte into the transmit stream.
• Extracts a 64 byte (Bellcore compatible) or 16 byte (ITU compatible) section trace (J0) message using an internal register bank for the receive stream. Detects an unstable message or mismatch message with an expected message. Provides access to the accepted message via the microprocessor port. Inserts a 64 byte or 16 byte section trace (J0) message using an internal register bank for the transmit stream.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line remote defect indication (RDI-L), line alarm indication signal (AIS-L), and protection switching byte failure alarms on the receive stream.
• Configurable to force Line AIS in the transmit stream.
• Provides automatic transmit line RDI insertion following detection of various received alarms (LOS, LOF, LAIS, SD, SF, STIM, STIU).
• Provides automatic DROP bus line AIS insertion following detection of various received alarms (LOS, LOF, LAIS, SD, SF, STIM, STIU).
• Support Automatic Protection Switching (APS) via a serial 4x777.76 LVDS mate protection port.
1.3 SONET Path / SDH High Order Path
• Interprets the received payload pointer (H1, H2) and extracts the STS-48c/STM-16c synchronous payload envelope and path overhead.
• Detects loss of pointer (LOP), path alarm indication signal (PAIS) and path (normal and enhanced) remote defect indication (RDI) for the receive stream. Optionally inserts path alarm indication signal (PAIS) and path remote defect indication (RDI) in the transmit stream.
• Extracts and insert the entire SONET/SDH path overhead to and from dedicated pins. The path overhead bytes may be sourced from internal registers or from bit serial path overhead input stream. Path overhead insertion may also be disabled.
• Extracts the received path payload label (C2) byte into an internal register and detects for payload label unstable (PLU), payload label mismatch (PLM), payload unequipped (UNEQ) and payload defect indication (PDI). Inserts the path payload label (C2) byte from an internal register for the transmit stream.
• Extracts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the receive stream. Detects an unstable message or mismatch message with an expected message. Provides access to the captured, accepted and expected message via the microprocessor port. Inserts a 64 byte or 16 byte path trace (J1) message using an internal register bank for the transmit stream.
• Detects received path BIP-8 and counts received path BIP-8 errors for performance monitoring purposes. BIP-8 errors are selectable to be treated on a bit basis or block basis. Optionally calculates and inserts path BIP-8 error detection codes for the transmit stream.
• Counts received path remote error indications (REI's) for performance monitoring purposes. Optionally inserts the path REI count into the path status byte (G1) based on bit or block BIP-8 errors detected in the receive path. Reporting of BIP-8 errors is on a bit or block basis independent of the accumulation of BIP-8 errors.
• Provides automatic transmit path RDI and path Enhanced RDI insertion following detection of various received alarms (LAIS, LOP, LOPCON, PAIS, PAISCON, PTIM, PTIU, PLM, PLU, UNEQ, PDI).
1.4 The Receive ATM Processor
• Extracts ATM cells from the received STS-48c/STM16-16c channel payloads using ATM cell delineation.
• Provides ATM cell payload de-scrambling.
• Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
• Detects out of cell delineation (OCD) and loss of cell delineation (LCD) alarms.
• Counts number of received cells, idle cells, erred cells and dropped cells.
• Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104 MHz) with parity support to read extracted cells from an internal 8 cell FIFO buffer.
1.5 The Receive POS Processor
• Supports packet based link layer protocols using byte synchronous HDLC framing.
• Performs self-synchronous POS data de-scrambling on the received STS-48c/STM16c-16c payloads using the x43+1 polynomial.
• Performs flag sequence detection and terminates the received POS frames.
• Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.
• Performs control escape de-stuffing or byte de-stuffing of the POS stream.
• Detects packet abort sequence.
• Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks those exceeding the maximum length as erred.
• Permits FCS stripping on the POS-PHY output data stream.
• Provides a SATURN POS-PHY Level 3 compliant 32-bit datapath interface (clocked up to 104 MHz) with parity support to read packet data from an internal 256 byte FIFO buffer.
1.6 The Transmit ATM Processor
• Provides idle/unassigned cell insertion.
• Optionally provides HCS generation/insertion, and ATM cell payload scrambling.
• Counts the number of transmitted cells.
• Provides UTOPIA Level 3 and POS-PHY Level 3 32-bit wide datapath interfaces (clocked up to 104 MHz) with parity support for writing cells into an internal channel FIFO.
1.7 The Transmit POS Processor
• Supports any packet based link layer protocol using byte synchronous and bit synchronous framing like PPP, HDLC and Frame Relay.
• Performs self-synchronous POS data scrambling using the 1+X43 polynomial.
• Encapsulates packets within a POS/HDLC frame.
• Performs flag sequence insertion.
• Performs byte stuffing for transparency processing.
• Optionally performs frame check sequence generation using the CRC-CCITT and CRC-32 polynomials.
• Aborts packets under the direction of the host or when the FIFO underflows.
• Provides a SATURN POS-PHY Level 3 compliant 32-bit wide datapath (clocked up to 104 MHz) with parity support to an internal FIFO buffer.

The PM5381 S/UNI-2488 SATURN User Network Interface is a monolithic integrated circuit that implements SONET/SDH processing, ATM mapping and Packet over SONET mapping functions at the STS-48 (STM-16-16c) 2488.32 Mbit/s rate.

The S/UNI-2488 PM5381 receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-2488 performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-2488 PM5381 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cells or POS frames.

When PM5381 used to implement an ATM UNI or NNI, the S/UNI-2488 frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be optionally dropped. Cells of PM5381 are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell of PM5381 payloads are descrambled and are written to a 8-cell FIFO buffer. The received cells PM5381 are read from the FIFO using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes.

When PM5381 used to implement packet transmission over a SONET/SDH link, the S/UNI-2488 extracts Packet over SONET (POS) frames from the SONET/SDH synchronous payload envelope. Frames are verified for correct construction and size. The control escape characters are removed. The frame check sequence of PM5381 is optionally verified for correctness and the extracted packets are placed in a receive FIFO. The received packets are read from the FIFO through a 32-bit POS-PHY Level 3 (clocked up to 104 MHz) system side interface. Valid and FCS errored packet counts of PM5381 are provided for performance monitoring. The S/UNI-2488 Packet over SONET implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.

The S/UNI-2488 PM5381  transmits SONET/SDH streams using a bit serial interface. The S/UNI-2488 synthesizes the transmit clock from a 155.52MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) PM5381 are also inserted. The S/UNI-2488 generates the payload pointer (H1, H2) and inserts the synchronous payload envelope that carries the ATM or POS frames. The S/UNI-2488 PM5381 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

When PM5381 used to implement an ATM UNI or NNI, ATM cells are written to an internal 8 cell FIFO using a 32-bit wide UTOPIA Level 3 (clocked up to 104 MHz) datapath interface. Idle/unassigned cells PM5381 are automatically inserted when the internal FIFO contains less than one complete cell. The S/UNI-2488 provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

When PM5381 used to implement a Packet over SONET/SDH link, the S/UNI-2488 inserts POS frames into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a 256-byte FIFO through a 32-bit SATURN POS-PHY Level 3 (clocked up to 104 MHz) system side interface. POS frames of PM5381  are built by inserting the flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring.

No line rate clocks are required directly by the S/UNI-2488 as PM5381  synthesizes the transmit clock and recovers the receive clock using a 155.52 MHz reference clock. The S/UNI-2488 outputs a differential PECL line data (TXD+/-).

The S/UNI-2488 PM5381 is configured, controlled and monitored via a generic 16-bit microprocessor bus interface. The S/UNI-2488 also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The S/UNI-2488 PM5381 is implemented in low power, +1.8 Volt, CMOS technology. It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V compatible pseudo-ECL (PECL). The S/UNI-2488 is packaged in a 416 pin UBGA package.