PM5365

` Integrates a SONET/SDH VT1.5/VT2/TU11/TU12 bit asynchronous mapper, a full featured M13 multiplexer with DS3 framer, and a SONET/SDH DS3 mapper in a single monolithic device for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams.
` Five fundamental modes of operation:
` Single STS-1, AU3 or TUG3 Bit Asynchronous VT1.5 or TU-11 Mapper with ingress or egress per tributary link monitoring for 28 T1s.
` DS3 M13 Multiplexer with ingress or egress per link monitoring for 28 T1s.
` Up to 28 DS3 multiplexed T1 streams are mapped as bit asynchronous VT1.5 virtual tributaries or TU-11 tributary units, providing a transmultiplexing ("transmux") function between DS3 and SONET/SDH with ingress or egress per tributary link monitoring for 28 T1s.
` Single STS-1, AU3 or TUG3 Bit Asynchronous VT2 or TU-12 Mapper with ingress or egress per tributary link monitoring for 21 E1s or 21 T1s.
` Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747 recommendation. This E1 mode of operation is restricted to using the serial clock and data system interfaces.
` Up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries can be passed between the line SONET/SDH bus and the SBI bus as transparent virtual tributaries with pointer processing.
` When adding and dropping T1 or E1 tributaries the mapper and demapper blocks allow for up to 28 VT1.5/TU11 or 21 VT2/TU12 tributaries to be processed from any tributary location within the full STS-3/STM-1. On the telecom DROP bus side this requires that the STS-3/STM-1 be in locked mode such that the J1 bytes immediately follow the C1 bytes.
` Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams, 63 E1 streams or 3 DS3 streams. This interface also supports transparent virtual tributaries when used with the SONET/SDH mapper.
` Provides jitter attenuation in the T1 or E1 receive and transmit directions.
` Provides two independent de-jittered T1 or E1 recovered clocks for system timing and redundancy.
` Provides an on-board programmable binary sequence generator and detector for error testing at DS3 rates. Includes support for patterns recommended in ITU-T O.151.
` Also provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and NxDS0 rates as recommended in ITU-T O.151 and O.152.
` Supports the M23 and C-bit parity DS3 formats.
` Standalone unchannelized DS3 framer mode for access to the entire DS3 payload.
` When configured to operate as a DS3 Framer, gapped transmit and receive clocks can be optionally generated for interface to link layer devices which only need access to payload data bits.
` DS3 Transmit clock source can be selected from either an external oscillator or from the receive side clock (loop-timed).
` Provides a SONET/SDH Add/Drop bus interface with integrated VT1.5, TU- 11, VT2 and TU-12 mapper for T1and E1 streams. Also provides a DS3 mapper.
` Register level compatibility with the PM8315 TEMUX, the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver and the PM8313 D3MX M13 Multiplexer/Demultiplexer.
` Provides a generic 8-bit microprocessor bus interface for configuration, control and status monitoring.
` Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes.
` Low power 2.5V/3.3V CMOS technology. All pins are 5V tolerant.
` 324-pin fine pitch PBGA package (23mm x 23mm). Supports industrial temperature range (-40oC to 85oC) operation.

The PM5365 VT/TU Mapper and M13 Multiplexer (TEMAP) is a feature-rich device for use in any applications requiring high density link termination over T1 channelized DS3 or T1 and E1 channelized SONET/SDH facilities.

The TEMAP PM5365 supports asynchronous multiplexing and demultiplexing of 28 DS1s into a DS3 signal as specified by ANSI T1.107 and Bell Communications Research TR-TSY-000009. PM5365 supports bit asynchronous mapping and demapping of 28 T1s or 21 E1s into SONET/SDH as specified by ANSI T1.105, Bell Communications Research GR-253-CORE and ITU-T Recommendation G.707. The TEMAP also supports mapping of 21 T1s into SDH via TU-12s. Up to 28 Transparent VT1.5s and TU-11s or 21 Transparent VT2s and TU-12s PM5365 can be transferred between the SONET/SDH interface and the SBI bus interface. Performance monitoring in either the ingress or egress direction for up to 28 T1s or 21 E1s in both SONET/SDH VT/TU mapper and M13 multiplexer modes.

Each T1 performance monitor of PM5365 detects and indicates the presence of Yellow and AIS patterns and also integrates Yellow, Red, and AIS alarms. T1 performance monitoring with accumulation of CRC-6 errors, framing bit errors, out-of-frame events, and changes of frame alignment is provided. Each E1 framer of PM5365 detects and indicates the presence of remote alarm and AIS patterns and also integrates Red and AIS alarms.

The E1 framers PM5365 support detection of various alarm conditions such as loss of frame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers also support reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal. E1 PM5365 performance monitoring with accumulation of CRC-4 errors, far end block errors and framing bit errors is provided.

PM5365 can also be configured as a DS3 framer, providing external access to the full DS3 payload, or a VT/TU mapper, providing access to unframed 1.544Mb/s and 2.048Mb/s links.

PRBS generation or detection is supported on a per T1 or E1 link basis. The TEMAP PM5365 can generate a low jitter transmit clock from a variety of clock references, and PM5365 also provides jitter attenuation in the receive path. Two low jitter recovered T1 clocks can be routed outside the TEMAP for network timing applications.

Serial PCM interfaces to each T1 PM5365 framer allow 1.544 Mbit/s ingress/egress system interfaces to be directly supported. A Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels of integration and dense interconnect. The SBI bus of PM5365 interconnects up to 84 T1s or 63 E1. The SBI allows transmit timing to be mastered by either the TEMAP or link layer device connected to the SBI bus. PM5365 interconnect allows up to 3 TEMAPs to be connected in parallel to provide the full complement of 84 T1s or 63 E1s of traffic. In addition to clear channel T1s and E1s the TEMAP can transport framed or unframed DS3 links over the SBI bus.

When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TEMAP accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications.

In the DS3 receive direction, the TEMAP frames to DS3 signals with a maximum average reframe time of 1.5 ms in the presence of 10-3 bit error rate and detects line code violations, loss of signal, framing bit errors, parity errors, C-bit parity errors, far end block errors, AIS, far end receive failure and idle code. The DS3 framer of PM5365 is an off-line framer, indicating both out of frame (OOF) and change of frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) PM5365 are still indicated while the framer is OOF, based on the previous frame alignment. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC channels are detected and are available through the microprocessor port. Error event accumulation is also PM5365 provided by the TEMAP. Framing bit errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, and far end block errors are accumulated. Error accumulation continues even while the off-line framers are indicating OOF. The counters are intended to be polled once per second, and are sized so as not to saturate at a 10-3 bit error rate. Transfer of count values of PM5365 to holding registers is initiated through the microprocessor interface.

In the DS3 transmit direction, the TEMAP inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters PM5365 and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals, Far End Receive Failure of PM5365 and idle signal can be inserted using either internal registers or can be configured for automatic insertion upon received errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M sub-frame)PM5365  is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity application. Transmit timing is from an external reference or from the receive direction clock.

The TEMAP PM5365 also supports diagnostic options which allow it to insert a Pseudo Random Binary Sequence (PRBS) into a DS3 payload and checked in the receive DS3 payload for bit errors. A fixed 100100. pattern is available for insertion directly into the B3ZS encoder for proper pulse mask shape verification.

When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams PM5365 are demultiplexed and multiplexed into and out of the DS3 signal. Bit stuffing and rate adaptation is performed. The C-bits are set appropriately, with the option of inserting DS2 loopback requests. Interrupts can be generated upon detection of loopback requests in the received DS3. AIS PM5365 may be inserted in the any of the 6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit parity is supported by generating a 6.3062723 MHz clock, which corresponds to a stuffing ratio of 100%.

Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI TI.107) frame formats. The maximum average reframe time of PM5365 is 7ms for DS2. Far end receive failure of PM5365 is detected and M-bit and F-bit errors are accumulated. The DS2 framer is an off-line framer, indicating both OOF and COFA events. Error events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated while the DS2 framer is indicating OOF, based on the previous alignment.

Each of the seven 6312 kbit/s multiplexers may be independently configured to multiplex and demultiplex four 1544 kbit/s DS1s into and out of a DS2 formatted signal. Tributary frequency deviations of PM5365 are accommodated using internal FIFOs and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1 loopback requests. Interrupts ofPM5365 can be generated upon detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both multiplex and demultiplex directions. When configured as a DS3 framer the unchannelized payload of the DS3 link is available to an external device.

The SONET/SDH line side interface provides STS-1 SPE synchronous payload envelope processing and generation, TUG3 tributary unit group processing and generation within a VC4 virtual container of PM5365  and VC3 virtual container processing and generation. The payload processor aligns and monitors the performance of SONET PM5365 virtual tributaries (VTs) or SDH tributary units (TUs). Maintenance functions per tributary include detection of loss of pointer, AIS alarm, tributary path signal label mismatch and tributary path signal label unstable alarms. Optionally interrupts can be generated due to the assertion and removal of any of the above alarms. Counts of PM5365 are accumulated for tributary path BIP-2 errors on a block or bit basis and for FEBE indications. The synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary path BIP-2. The generator also inserts FEBE, RDI and enhanced RDI in the V5 byte. Software can force AIS insertion on a per tributary basis.

A SONET/SDH mapper maps of PM5365 and demaps up to 28 T1s, 21 E1s or a single DS3 into a STS-1 SPE, TUG3 or VC3 through an elastic store. The fixed stuff (R) bits of PM5365 are all set to zeros or ones under microprocessor control. The bit asynchronous demapper performs majority vote C-bit decoding to detect stuff requests for T1, E1 and DS3 asynchronous mappings. The VT1.5/VT2/TU-11/TU-12 mapper uses an elastic store and a jitter attenuator capability to minimize jitter introduced via bit stuffing.

The TEMAP PM5365 is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface.