PM5362

Features: · Configurable, multi-channel, payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial data stream.· Transfers all incoming tributaries in the three STS-1 synchronous payload envelopes of an STS-3 byte serial stream to ...

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SeekIC No. : 004463695 Detail

PM5362: Features: · Configurable, multi-channel, payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial data stream.· Transfers all inco...

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Part Number:
PM5362
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/25

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Product Details

Description



Features:

· Configurable, multi-channel, payload processor for aligning SONET virtual tributaries (VTs) or SDH tributary units (TUs) in an STS-3 or STM-1 byte serial data stream.
· Transfers all incoming tributaries in the three STS-1 synchronous payload envelopes of an STS-3 byte serial stream to the three STS-1 synchronous payload envelopes of an outgoing STS-3 byte serial stream.
· Transfers all incoming tributaries in the single AU4 or three AU3 administrative units of an STM-1 byte serial stream to the single AU4 or three AU3 administrative units of an outgoing STM-1 byte serial stream.
· Compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) payload frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, or TU11) tributary pointers.
· Configurable to process any legal mix of tributaries such as VT1.5, VT2, VT3, VT6, TU11, TU12, TU2, or TU3. Each VT group or TUG2 can be configured to carry one of four tributary types. TUG2s can be multiplexed into VC3s or TUG3s. Each TUG3 can also be configured to carry a single TU3.
· Independently configurable for AU3 or AU4 frame format on incoming and outgoing interfaces.
· Configurable to process 16-byte or 64-byte format tributary path trace messages (tributary trail trace identifiers).
· Optionally frames to the H4 byte in the path overhead to determine tributary multiframe boundaries. Inserts internally generated H4 bytes with leading logic 1 bits into the outgoing administrative units.
· Extracts and serializes the entire tributary path overhead for each tributary into lower speed serial streams.
· Extracts tributary size (SS) bits for each tributary into internal registers.
· Detects loss of pointer (LOP) and re-acquisition for each tributary and optionally generates interrupts.
· Detects tributary path alarm indication signal (AIS) and return to normal state for each tributary and optionally generates interrupts.
· Detects tributary elastic store underflow and overflow errors and optionally generates interrupts.
· Extracts tributary path trace message (trail trace identifier) for each tributary into internal buffers.
· Provides individual tributary path trace message buffer that holds the expected message and detects tributary path trace mismatch (trail trace identifier mismatch) alarms (TIM) and return to matched state for each tributary and optionally generates interrupts.
· Detects tributary path trace unstable (trail trace identifier unstable) alarms (TIU) and return to stable state for each tributary and optionally generates interrupts.
· Extracts tributary path signal label for each tributary into internal registers and detects change of tributary path signal label events (COPSL) for each tributary and optionally generates interrupts.
· Provides individual tributary path signal label register that hold the expected label and detects tributary path signal label mismatch alarms (PSLM) and return to matched state for each tributary and optionally generates interrupts.
· Detects tributary path signal label unstable alarms (PSLU) and return to stable state for each tributary and optionally generates interrupts.
· Detects tributary unequipped defect (UNEQ) and tributary path defect indication (PDI-V).
· Detects assertion and removal of tributary extended remote defect indications (RDI) for each tributary and optionally generates interrupts.
· Calculates and compares the tributary path BIP-2 error detection code for each tributary and configurable to accumulate the BIP-2 errors, on block or bit basis, in internal registers.
· Calculates and compares the TU3 path BIP-8 error detection code for each TU3 stream and accumulates the BIP-8 errors, on block or bit basis, in internal registers.
· Accumulates TU3 tributary far end block errors (FEBE) on a bit or a block basis, in internal registers.
· Allows insertion of all-zeros or all-ones tributary idle code with unequipped indication and valid pointer into any tributary under software control. Idle tributaries are identified by an output signal.
· Identifies outgoing tributaries that are in AIS state by an output signal. Allows software to force the AIS insertion on a per tributary basis.
· Inserts valid H4 byte and all-zeros fixed stuff bytes on the outgoing stream. Remaining path overhead bytes (J1, B3, C2, G1, F2, Z3, Z4, and Z5) can be configured to be set to all-zeros or to reflect the value of the corresponding POH bytes in the incoming stream.
· Inserts valid pointers, and all-zeros transport overhead bytes on the outgoing stream with valid "TeleCombus" control signals when configured to operate in locked mode.
· Supports in-band error reporting by updating the FEBE, RDI and auxiliary RDI bits in the V5 byte (G1 in TU3) with the status of the incoming stream.
· Provides low maximum tributary processing delay of 33 µs for VT1.5, 25 µs for VT2, 17 µs for VT3, and 9 µs for VT6 streams.
· Verifies parity on the IC1J1 and ISPE signals and on the incoming data stream and generates parity on the outgoing data stream.
· May be used for multiframe synchronization or ring closure at the head-end node of a SONET/SDH ring.
· Operates in conjunction with the PM5344 SPTX SONET/SDH Path Terminating Transceiver to align tributaries such that they can be switched by the PM5371 TUDX SONET/SDH Tributary Unit Cross-Connect. Provides backwards compatibility with the PM5361 TUPP SONET/SDH Tributary Unit Payload Processor.
· Independently configurable incoming and outgoing interfaces that operate in byte interface mode from a single 19.44 MHz clock or in nibble interface mode from a single 38.88 MHz clock.
· Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
· Provides a standard 5 signal IEEE P1149.1 JTAG test port for boundary scan test purposes.
· Low power, +5 Volt, CMOS technology, TTL compatible inputs and outputs.
· 160 pin plastic quad flat pack (PQFP) package




Application

· SONET/SDH Wideband Cross-Connect
· SONET/SDH Add-Drop Multiplexer



Pinout

  Connection Diagram


Specifications

Ambient Temperature under Bias -40°C to +85°C
Storage Temperature -40°C to +125°C
Supply Voltage -0.5V to +6.0V
Voltage on Any Pin -0.5V to VDD+0.5V
Static Discharge Voltage ±1000 V
Latch-Up Current ±100 mA
DC Input Current ±20 mA
Lead Temperature +220°C
Absolute Maximum Junction Temperature +150°C
Power Dissipation 1.5 W



Description

The PM5362 TUPP-PLUS SONET/SDH Tributary Unit Payload Processor /Performance Monitor is a monolithic integrated circuit that implements a configurable, multi-channel, payload processor that aligns and monitors performance of SONET virtual tributaries (VTs) or SDH tributary units (TUs.).

When configured for SONET compatible operation, the TUPP-PLUS PM5362 transfers all tributaries in the three STS-1 synchronous payload envelopes of an incoming STS-3 byte serial stream to the three STS-1 synchronous payload envelopes of an outgoing STS-3 byte serial stream. Similarly, when PM5362 configured for SDH compatible operation, the TUPP-PLUSPM5362  transfers all tributaries in the single AU4 or three AU3 administrative units of an incoming STM-1 byte serial stream to a single AU4 or three AU3 administrative units of an outgoing STM-1 byte serial stream. The TUPP-PLUS compensates for pleisiochronous relationships between incoming and outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing of the lower level (VT6, VT3, VT2, VT1.5, TU3, TU2, TU12, TU11) tributary pointers.

The TUPP-PLUS  PM5362 is configurable to process any legal mix of tributaries. Each VT group can be configured to carry any one of the four tributary types (VT1.5, VT2, VT3, or VT6) and each TUG2 can be configured to carry any one of three tributary types (TU11, TU12, or TU2). TUG2s can be multiplexed into a VC3 or a TUG3. Alternatively, each TUG3 can be configured to carry a TU3.

The TUPP-PLUS PM5362 operates in conjunction with the PM5344 SONET/SDH Path Terminating Transceiver to align tributaries such that they can be switched by the PM5371 TUDX SONET/SDH Tributary Unit Cross-Connect.

The TUPP-PLUS PM5362 provides useful maintenance functions. PM5362 include, for each tributary, detection of loss of pointer, detection of AIS alarm, detection of tributary path signal label mismatch and unstable alarms, detection of tributary path trace mismatch and unstable alarms. Optionally, interrupts can be generated due to the assertion and removal of any of the above alarm conditions. The TUPP-PLUS PM5362 counts received tributary path BIP-2 (BIP-8 for TU3) errors on a block or bit basis and counts FEBE indications. The TUPP-PLUS also allows insertion of tributary path AIS as a consequence of any of the above alarm conditions. In addition, the TUPP-PLUS PM5362 may insert tributary idle (unequipped) into any tributary. Incoming tributary path trace messages and path signal labels are stored in a set of microprocessor accessible registers. The TUPP-PLUS can also insert inverted new data flag fields that can be used to diagnose downstream pointer processing elements.

No auxiliary high speed clocks are required as the TUPP-PLUS operates from either a single 19.44 MHz or a single 38.88 MHz line rate clock. The TUPP-PLUS PM5362 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.

The TUPP-PLUS PM5362 is implemented in low power, +5 Volt, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 160 pin HPPQFP package.




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