PM5357

1.1 General
• Single chip ATM and Packet over SONET/SDH Physical Layer Device operating at 622.08 Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 2615.
• Processes duplex bit-serial 622.08 Mbit/s STS-12c/STM-4-4c data streams with on-chip clock and data recovery and clock synthesis.
• Supports a duplex byte-serial 77.76 Mbyte/s STS-12c/STM-4-4c line side interface for use in applications where by-passing clock recovery, clock synthesis, and serializer-deserializer functionality is desired.
• Supports a byte-serial 19.44 Mbyte/s STS-3c/STM-1 line side interface on the transmit and/or receive interface for use in applications where a 155.52 Mbit/s data rate is desired.
• Supports clock recovery by-pass for use in applications where external clock recovery is desired.
• Complies with Bellcore GR-253-CORE (1995 Issues) jitter tolerance, jitter transfer and intrinsic jitter criteria.
• Provides control circuitry required to comply with Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
• Provides UTOPIA Level 2 16-bit wide System Interface (clocked up to 50 MHz) with parity support for ATM applications.
• Provides UTOPIA Level 3 compatible 8-bit wide System Interface (clocked up to
100 MHz) with parity support for ATM applications.
• Provides SATURN POS-PHY Level 2 16-bit System Interface (clocked up to 50 MHz) for Packet over SONET/SDH (POS) applications. This system interface is similar to UTOPIA Level 2, but adapted to packet transfer.
• Provides SATURN POS-PHY Level 3 8-bit System Interface (clocked up to 100 MHz) for Packet over SONET/SDH (POS) applications.
• Provides support functions for a two chip solution for 1+1 APS operation.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
• Low power 3.3V CMOS with TTL compatible digital inputs and CMOS/TTL digital outputs. PECL inputs and outputs are 3.3V and 5V compatible.
• Industrial temperature range (-40°C to +85°C).
• 304 pin Super BGA package.
1.2 The SONET Receiver
• Provides a serial interface at 622.08 Mbit/s with clock and data recovery.
• Frames to and de-scrambles the received STS-12c/STM-4-4c stream.
• Optionally frames to and de-scrambles a received STS-3c/STM-1 stream.
• Interprets the received payload pointer (H1, H2) and extracts the STS-12c/STM- 4-4c or STS-3c/STM-1 synchronous payload envelope and path overhead.
• Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing.
• Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure.
• Captures and de-bounces the synchronization status (S1) nibble in a readable register.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
• Extracts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or 64-byte path trace (J1) sequence into internal register banks.
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS-L), line remote defect indication (RDI-L), loss of pointer (LOP), path alarm indication signal (AIS-P), path remote defect indication (RDIP), path extended remote defect indicator (extended RDI-P).
• Counts received section BIP-8 (B1) errors, received line BIP-96 (B2) errors, line remote error indicates (REI-L), received path BIP-8 (B3) errors and path remote error indications (REI-P) for performance monitoring purposes.
1.3 The Receive ATM Processor
• Extracts ATM cells from the received STS-12c/STM-4-4c or STS-3c/STM-1 payload using ATM cell delineation.
• Provides ATM cell payload de-scrambling.
• Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
• Detects out of cell Delineation (OCD) and loss of cell delineation (LCD) alarms.
• Counts number of received cells, idle cells, errored cells and dropped cells.
• Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer.
• Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support to read extracted cells from an internal four-cell FIFO buffer.
1.4 The Receive POS Processor
• Supports packet based link layer protocols using byte synchronous HDLC framing like PPP, HDLC and Frame Relay.
• Performs self-synchronous POS data de-scrambling on the received STS- 12c/STM-4-4c or STS-3c/STM-1 payload using the x43+1 polynomial.
• Performs flag sequence detection and terminates the received POS frames.
• Performs frame check sequence (FCS) validation for CRC-CCITT and CRC-32 polynomials.
• Performs control escape de-stuffing of the HDLC stream.
• Detects for packet abort sequence.
• Checks for minimum and maximum packet lengths. Optionally deletes short packets and marks those exceeding the maximum length as errored.
• Provides a SATURN POS-PHY Level 2 compliant 16-bit datapath interface (clocked up to 50 MHz) with parity support to read packet data from an internal 256 byte FIFO buffer.
• Provides a SATURN POS-PHY Level 3 compliant 8-bit datapath interface (clocked up to 100 MHz) with parity support to read packet data from an internal 256 byte FIFO buffer.
1.5 The SONET Transmitter
• Synthesizes the 622.08 MHz transmit clock from a 77.76 MHz reference.
• Provides a differential PECL bit-serial interface at 622.08 Mbit/s.
• Inserts a register programmable path signal label (C2).
• Generates the transmit payload pointer (H1, H2) and inserts the path overhead.
• Optionally inserts the 16-byte or 64-byte section trace (J0/Z0) sequence and the 16-byte or 64-byte path trace (J1) sequence from internal register banks.
• Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream.
• Scrambles the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 stream and inserts the framing bytes (A1, A2).
• Optionally inserts register programmable APS bytes.
• Provides a byte-serial transmit path data stream allowing two devices to implement 1+1 APS.
• Inserts path BIP-8 codes (B3), path remote error indications (REI-P), line BIP-96 codes (B2), line remote error indications (REI-L), and section BIP-8 codes (B1) to allow performance monitoring at the far end.
• Allows forced insertion of all-zeros data (after scrambling) and the corruption of the section, line, or path BIP-8 codes for diagnostic purposes.
• Inserts ATM cells or POS frames into the transmitted STS-12c/STM-4-4c or STS-3c/STM-1 payload.
1.6 The Transmit ATM Processor
• Provides idle/unassigned cell insertion.
• Provides HCS generation/insertion, and ATM cell payload scrambling.
• Counts number of transmitted and idle cells.
• Provides a UTOPIA Level 2 compliant 16-bit wide datapath interface (clocked up to 50 MHz) with parity support for writing cells into an internal four-cell FIFO.
• Provides a UTOPIA Level 3 compatible 8-bit wide datapath interface (clocked up to 100 MHz) with parity support for writing cells into an internal four-cell FIFO.
1.7 The Transmit POS Processor
• Supports any packet based link layer protocol using byte synchronous HDLC framing like PPP, HDLC and Frame Relay.
• Performs self-synchronous POS data scrambling using the 1+X43 polynomial.
• Encapsulates packets within a POS frame.
• Performs flag sequence insertion.
• Performs byte stuffing for transparency processing.
• Performs frame check sequence generation using the CRC-CCITT and CRC-32 polynomials.
• Aborts packets under the direction of the host or when the FIFO underflows.
• Provides a SATURN POS-PHY Level 2 compliant 16-bit wide datapath (clocked up to 50 MHz) with parity support to an internal 256 byte FIFO buffer.
• Provides a SATURN POS-PHY Level 3 compliant 8-bit wide datapath (clocked up to 100 MHz) with parity support to an internal 256 byte FIFO buffer.

The PM5357 S/UNI-622-POS SATURN User Network Interface is a monolithic integrated circuit that implements SONET/SDH processing, ATM mapping and Packet over SONET/SDH mapping functions at the STS-12c/STM-4-4c 622.08 Mbit/s rate.

The S/UNI-622-POS PM5357 receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-622-POS can also be configured for clock and data recovery and clock synthesis by-pass where PM5357 receives SONET/SDH PM5357 frames via a byte-serial interface. The S/UNI-622-POS PM5357 performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path remote error indications (M1, G1) are also accumulated. The S/UNI-622-POS interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload.

When PM5357 used to implement an ATM UNI or NNI, the S/UNI-622-POS frames to the ATM payload using cell delineation. HCS error correction is provided.

Idle/unassigned cells may be optionally dropped. Cells are also dropped upon detection of PM5357 of an uncorrectable header check sequence error. The ATM cell PM5357 payloads are descrambled and are written to a four-cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and those that are errored and correctable are accumulated independently for performance monitoring purposes.

When PM5357 used to implement packet transmission over a SONET/SDH link, the S/UNI-622-POS extracts Packet over SONET/SDH (POS) frames from the SONET/SDH synchronous payload envelope. Frames of PM5357 are verified for correct construction and size. The control escape characters are removed. The frame check sequence of PM5357 is optionally verified for correctness and the extracted packets of PM5357 are placed in a receive FIFO. The received packets are read from the FIFO through a 16-bit POS-PHY Level 2 (clocked up to 50 MHz) or an 8-bit POS-PHY Level 3 (clocked up to 100 MHz) system side interface. Valid and FCS errored packet counts are provided for performance monitoring. The S/UNI-622-POS Packet over SONET/SDH implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.

The S/UNI-622-POS PM5357 transmits SONET/SDH streams using a bit serial interface. The S/UNI-622-POS PM5357 can also be configured for clock and data recovery and clock synthesis by-pass where it transmits the SONET/SDH frames via a byteserial interface. The S/UNI-622-POS synthesizes of PM5357 the transmit clock from a 77.76MHz frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity codes (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path remote error indications (M1, G1) are also inserted. The S/UNI-622-POS generates the payload pointer (H1, H2) and inserts the synchronous payload envelope that carries the POS frame payload.

The S/UNI-622-POSPM5357  also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

When PM5357 used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide UTOPIA Level 3 (clocked up to 100 MHz) datapath interface.

Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one complete cell. The S/UNI-622-POS PM5357 provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions of PM5357 can be enabled or bypassed.

When PM5357 used to implement a Packet over SONET/SDH link, the S/UNI-622-POS inserts POS frames into the SONET/SDH synchronous payload envelope.

Packets of PM5357 to be transmitted are written into a 256-byte FIFO through a 16-bit SATURN POS-PHY Level 2 (clocked up to 50 MHz) or an 8-bit SATURN POSPHY Level 3 (clocked up to 100 MHz) system side interface. POS frames of PM5357 are built by inserting the flags, control escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring.

No line rate clocks of PM5357 are required directly by the S/UNI-622-POS as PM5357 synthesizes the transmit clock and recovers the receive clock using a 77.76 MHz reference clock. The S/UNI-622-POS outputs a differential PECL line data (TXD+/-). The S/UNI-622-POS also provides a WAN Synchronization controller that can be used to control an external VCXO in order to fully meet Bellcore GR-253-CORE jitter, wander, holdover and stability requirements.

The S/UNI-622-POS PM5357 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-622-POS also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The S/UNI-622-POS PM5357 is implemented in low power, +3.3 Volt, CMOS technology. It has TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). The S/UNI-622-POS is packaged in a 304 pin SBGA package.