PM5355

· Monolithic Saturn User Network Interface that implements the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432 and the ATM Forum BISDN Inter Carrier Interface (B-ICI) Specification.
· Supports a 77.76 Mbyte/s STS-12c (STM-4c), a 19.44 Mbyte/s STS-3c (STM-1), a 6.48 Mbyte/s STS-1, or a 51.84 Mbit/s STS-1 line side interface.
· Provides four-cell deep FIFO buffers in both the transmit and receive paths.
· Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
· Provides a generic parallel output port and a generic parallel input port to control and monitor front end line devices.
· Provides a standard 5-signal P1149.1 JTAG test port for boundary scan board test purposes.
· Low-power, +5 Volt, CMOS technology.
· 208-pin high-performance plastic quad flat pack (PQFP) package.
1.1 The receiver section:
· Frames to and descrambles the received STS-12c/3c/1 (STM-4c/1, AU-3) stream.
· Filters and captures the automatic protection switch channel (APS) bytes in readable registers and detects APS byte failure.
· Interprets the received payload pointer (H1, H2) and extracts the STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope and path overhead.
· Extracts ATM cells from the received STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope using ATM cell delineation and provides optional ATM cell payload descrambling, header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
· Provides a generic 16-bit wide datapath interface to read extracted cells from an internal four-cell FIFO buffer.
· Extracts all transport overhead bytes and serializes them in four 5.184 Mbit/s streams for optional external processing.
· Extracts the section user channel (F1) and the order wire channels (E1, E2) and serializes them into three independent 64 kbit/s streams for optional external processing.
· Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing.
· Extracts all path overhead bytes and serializes them at 576 kbit/s for optional external processing.
· Extracts the 16- or 64-byte section trace (C1) sequence and the 16- or 64- byte path trace (J1) sequence into internal register banks.
· Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication signal (RDI-P) and loss of cell delineation (LCD).
· Counts received section BIP-8 (B1) errors, received line BIP-96/24/8 (B2) errors, line far end block errors (line FEBEs), received path BIP-8 (B3) errors and path far end block errors (path FEBEs) for performance monitoring purposes.
· Counts received cells written into the receive FIFO, received HCS errored cells that are discarded, and received HCS errored cells that are corrected and passed on.
· Extracts and serializes the GFC field from all received cells (including idle/unassigned cells) for external processing.
1.2 The transmitter section:
· Provides an internal four-cell FIFO into which cells are written using a generic 16-bit wide datapath interface.
· Inserts the generic flow control (GFC) bits via a simple serial interface.
· Counts transmit cells read from the transmit FIFO.
· Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM cell payload scrambling.
· Inserts ATM cells into the transmitted STS-12c/3c/1 (STM-4c/1, AU-3) synchronous payload envelope.
· Inserts a register programmable path signal label.
· Generates the transmit payload pointer (H1, H2) and inserts the path overhead.
· Optionally inserts the 16- or 64-byte section trace (C1) sequence and the 16- or 64-byte path trace (J1) sequence from internal register banks.
· Optionally inserts externally generated path overhead bytes received via a 576 kbit/s serial interface.
· Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream.
· Optionally inserts externally generated section user channel (F1) and externally generated order wire channels (E1, E2) via three 64 kbit/s serial interfaces.
· Optionally inserts externally generated transport overhead bytes received via four 5.184 Mbit/s serial interfaces.
· Scrambles the transmitted STS-12c/3c/1 (STM-4c/1, AU-3) stream and inserts the framing bytes (A1, A2) and the identity byte (C1).
· Optionally inserts path alarm indication signal (AIS), path remote defect indication (RDI-P), line alarm indication signal (AIS) and line remote defect indication (LRDI) indication.
· Optionally inserts register programmable APS bytes.
· Inserts path BIP-8 codes (B3), path far end block error (FEBE) indications, line BIP-96/24/8 codes (B2), line far end block error (FEBE) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.
· Allows forced insertion of all-zeros data (after scrambling), the corruption of the framing bytes or the corruption of the section, line, or path BIP-8 codes for diagnostic purposes.

The PM5355 S/UNI-622 SATURN User Network Interface is a monolithic  integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 622-Mbit/s ATM User Network Interface.

The S/UNI-622 receives SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1), and processes section, line, and path overhead. PM5355 performs framing (A1, A2), performs descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (Z2, G1) are also accumulated. The S/UNI-622 PM5355 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. In addition to basic processing of the received SONET/SDH PM5355 overhead, the S/UNI-622 provides convenient access to all overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired.

The S/UNI-622 frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell PM5355 payloads are descrambled. The ATM cells PM5355 that are passed are written to a four-cell FIFO buffer. The received cells are read from the FIFO using a generic 16-bit wide datapath interface. Counts of errored received ATM cell headers that are uncorrectable and those that PM5355 are correctable are accumulated independently for performance monitoring purposes.

The S/UNI-622 transmits SONET/SDH frames via a byte-serial interface (or bitserial interface for STS-1) and formats section, line, and path overhead appropriately. PM5355 performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (Z2, G1) are also inserted. The S/UNI-622 generates the payload pointer (H1, H2) and inserts the synchronous payload envelope of PM5355 which carries the ATM cell payload. In addition to the basic formatting of the transmitted SONET/SDH overhead, the S/UNI-622 provides convenient access to all overhead bytes, which are optionally inserted from lower rate serial interfaces, allowing external sourcing of overhead, if desired. The S/UNI-622 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors of PM5355, and illegal pointers, which are useful for system diagnostics and tester applications.

ATM cells PM5355 are written to an internal four-cell FIFO using a generic 16-bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. Generic flow control PM5355 (GFC) bits may be inserted downstream of the FIFO via a serial link so that all FIFO latency may be bypassed. The S/UNI-622 provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

No auxiliary clocks are required directly by the S/UNI-622 since PM5355 operates from two line clocks. The S/UNI-622 is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-622 also provides a standard 5-signal P1149.1 JTAG test port of PM5355 for boundary scan board test purposes.

The S/UNI-622 is implemented in low-power, +5 Volt, CMOS technology. PM5355 has TTL compatible inputs and outputs and is packaged in a 208-pin PQFP package.