PM5352

1.1 General
• Single chip ATM User-Network Interface operating at 155.52 Mbit/s.
• Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
• Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).
• Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip clock and data recovery and clock synthesis.
• Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
• Exceeds Bellcore GR-253-CORE jitter transfer and phase variation criteria.
• Provides control circuitry required to exceed Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
• Compatible with ATM Forum's Utopia Level 2 Specification with Multi- PHY addressing and parity support.
• Implements the POS-PHY 16-bit System Interface for Packet over SONET/SDH (POS) applications. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.
• Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
• Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
• Low power 3.3V CMOS with PECL and TTL compatible inputs and CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).
• Industrial temperature range (-40°C to +85°C).
• 304 pin Super BGA package.
1.2 The SONET Receiver
• Provides a serial interface at 155.52 Mbit/s.
• Recovers the clock and data.
• Frames to and de-scrambles the recovered stream.
• Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
• Captures and debounces the synchronization status (S1) byte in a readable register.
• Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure.
• Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors, line far end block errors (FEBE), and received path BIP-8 (B3) errors and path far end block errors (FEBE).
• Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (LAIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (PAIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).
• Extracts the section and line data communication channels (D1-D3 and D4-12) as selected in internal register banks and serializes them at 192 Kbit/s (D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.
• Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence into internal register banks.
• Interprets the received payload pointer (H1, H2) and extracts the STS- 3c (STM-1) synchronous payload envelope and path overhead.
• Provides a divide by 8 recovered clock (19.44 MHz).
• Provides a 8KHz receive frame pulse.
1.3 The Receive ATM Processor
• Extracts ATM cells from the received STS-3c (STM-1) synchronous payload envelope using ATM cell delineation.
• Provides ATM cell payload de-scrambling.
• Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
• Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
• Counts number of received cells, idle cells, errored cells and dropped cells.
• Provides a synchronous 8-bit wide, four-cell FIFO buffer.
1.4 The Receive POS Processor
• Generic design that supports packet based link layer protocols, like PPP, HDLC and Frame Relay.
• Performs self synchronous POS data de-scrambling on SPE payload (x43+1 polynomial).
• Performs flag sequence detection and terminates the received POS frames.
• Performs frame check sequence (FCS) validation. The POS processor supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
• Performs Control Escape de-stuffing.
• Checks for packet abort sequence.
• Checks for octet aligned packet lengths and for minimum and maximum packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored.
• Provides a synchronous 256 byte FIFO buffer accessed through a 16- bit data bus on the POS-PHY System Interface.
1.5 The SONET Transmitter
• Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
• Provides a differential TTL serial interface (can be adapted to PECL levels) at 155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).
• Provides a transmit frame pulse input to align the transport frames to a
system reference.
• Provides a transmit byte clock (divide by eight of the synthesized line rate clock) to provide a timing reference for the transmit outputs.
• Optionally inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
• Optionally inserts path alarm indication signal (PAIS), path remote defect indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).
• Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.
• Optionally inserts the section and line data communication channels (D1-D3 or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.
• Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence from internal register banks.
• Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing bytes (A1,A2).
• Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1) synchronous payload envelope.
1.6 The Transmit ATM Processor
• Provides idle/unassigned cell insertion.
• Provides HCS generation/insertion, and ATM cell payload scrambling.
• Counts number of transmitted and idle cells.
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
1.7 The Transmit POS Processor
• Generic design that supports any packet based link layer protocol, like PPP, HDLC and Frame Relay.
• Performs self synchronous POS data scrambling (X43 + 1 polynomial).
• Encapsulates packets within a POS frame.
• Performs flag sequence insertion.
• Performs byte stuffing for transparency processing.
• Performs frame check sequence generation. The POS processor supports the generation of both CRC-CCITT and CRC-32 frame check sequences.
• Aborts packets under the direction of the host or when the FIFO underflows.
• Provides a synchronous 256 byte FIFO buffer accessed through the16-bit data bus on the POS-PHY System Interface.

Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins of PM5352 and the data bus to be held in a high-impedance state.= This test feature may be used for board testing.

PM5352 registers are used to apply test vectors during production testing of the S/UNI-STAR. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[10]) is high.

Test mode registers of PM5352 may also be used for board testing. When all of the TSBs within the S/UNI-STAR are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details).

In addition, the S/UNI-STAR also supports a standard IEEE 1149.1 fivesignal JTAG boundary scan test port of PM5352 for use in board testing. All digital device inputs may be read and all digital device outputs may be forced via the JTAG test port.