PM5351

1.1 General
` Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.
` Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
` Implements the Point-to-Point Protocol (PPP) over SONET/SDH specification according to RFC 1619/1662 of the PPP Working Group of the Internet Engineering Task Force (IETF).
` Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip clock and data recovery and clock synthesis.
` Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
` Exceeds Bellcore GR-253-CORE (1995 Issue) jitter transfer and phase variation criteria.
` Provides control circuitry required to exceed Bellcore GR-253-CORE WAN clocking requirements related to wander transfer, holdover and long term stability when using an external VCXO.
` Fully implements the ATM Forum's Utopia Level 2 Specification with Multi- PHY addressing and parity support.
` Implements the POS-PHY 16-bit System Interface for Packet over SONET/SDH (POS) applications. This system interface is similar to Utopia Level 2, but adapted to packet transfer. Both byte-level and packet-level transfer modes are supported.
` Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
` Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
` Low power 3.3V CMOS with PECL and TTL compatible inputs and CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).
` Industrial temperature range (-40°C to +85°C).
` 304 pin Super BGA package.
1.2 The SONET Receiver
` Provides a serial interface at 155.52 Mbit/s.
` Recovers the clock and data.
` Frames to and de-scrambles the recovered stream.
` Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
` Captures and debounces the synchronization status (S1) byte in a readable register.
` Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure.
` Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors, line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).
` Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (AIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (AIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).
` Extracts the section and line data communication channels (D1-D3 and D4-12) as selected in internal register banks and serializes them at 192 Kbit/s (D1-D3) and 576 Kbit/s (D4-D12) for optional external processing.
` Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence into internal register banks.
` Interprets the received payload pointer (H1, H2) and extracts the STS-3c (STM-1) synchronous payload envelope and path overhead.
` Provides individual divide by 8 recovered clocks (19.44 MHz) for each channel.
` Provides individual 8KHz receive frame pulses for each channel.
1.3 The Receive ATM Processor
` Extracts ATM cells from the received STS-3c (STM-1) synchronous payload envelope using ATM cell delineation.
` Provides ATM cell payload de-scrambling.
` Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
` Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
` Counts number of received cells, idle cells, errored cells and dropped cells.
` Provides a synchronous 8-bit wide, four cell FIFO buffer.
1.4 The Receive POS Processor
` Generic design that supports packet based link layer protocols, like PPP, HDLC and Frame Relay.
` Performs self synchronous POS data de-scrambling on SPE payload (x43+1 polynomial).
` Performs flag sequence detection and terminates the received POS frames.
` Performs frame check sequence (FCS) validation. The POS processor supports the validation of both CRC-CCITT and CRC-32 frame check sequences.
` Performs Control Escape de-stuffing.
` Checks for packet abort sequence.
` Checks for octet aligned packet lengths and for minimum and maximum packet lengths. Automatically deletes short packets (software configurable), and marks those exceeding the maximum length as errored.
` Provides a synchronous 256 byte FIFO buffer accessed through a 16-bit data bus on the POS-PHY System Interface.
1.5 The SONET Transmitter
` Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
` Provides a differential TTL serial interface (can be adapted to PECL levels) at 155.52 Mbit/s with both line rate data (TXD+/-) and clock (TXC+/-).
` Provides a single transmit frame pulse input across the four channels to align the transport frames to a system reference.
` Provides a single transmit byte clock (divide by eight of the synthesized line rate clock) to provide a timing reference for the transmit outputs.
` Optionally inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
` Optionally inserts path alarm indication signal (PAIS), path remote defect indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).
` Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.
` Optionally inserts the section and line data communication channels (D1-D3 or D4-12) via a 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) serial stream.
` Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence from internal register banks.
` Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing bytes (A1,A2).
` Inserts ATM cells or POS frames into the transmitted STS-3c (STM-1) synchronous payload envelope.
1.6 The Transmit ATM Processor
` Provides idle/unassigned cell insertion.
` Provides HCS generation/insertion, and ATM cell payload scrambling.
` Counts number of transmitted and idle cells.
` Provides a synchronous 8-bit wide, four cell FIFO buffer.
1.7 The Transmit POS Processor
` Generic design that supports any packet based link layer protocol, like PPP, HDLC and Frame Relay.
` Performs self synchronous POS data scrambling (X43 + 1 polynomial).
` Encapsulates packets within a POS frame.
` Performs flag sequence insertion.
` Performs byte stuffing for transparency processing.
` Performs frame check sequence generation. The POS processor supports the generation of both CRC-CCITT and CRC-32 frame check sequences.
` Aborts packets under the direction of the host or when the FIFO underflows.
` Provides a synchronous 256 byte FIFO buffer accessed through the16-bit data bus on the POS-PHY System Interface.

The PM5351 S/UNI-TETRA SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET/SDH processing, ATM mapping and Packet over SONET/SDH mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate.

The S/UNI-TETRA receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. PM5351 performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M1, G1) are also accumulated. The S/UNI-TETRA PM5351 interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell or POS packet payload. When used to implement an ATM UNI or NNI, the S/UNI-TETRA frames to the ATM payload using cell delineation. HCS error correction of PM5351 is provided. Idle/unassigned cells of PM5351 may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell of PM5351  payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide Utopia level 2 compliant datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes.

When PM5351 used to implement packet transmission over a SONET/SDH link, the S/UNI-TETRA extracts Packet over SONET/SDH (POS) frames from the SONET/SDH synchronous payload envelope. Frames are verified for correct construction of PM5351 and size. The Control Escape characters are removed. The error check sequence is optionally verified for correctness and the extracted packets are placed in a receive FIFO. The received packets of PM5351 are read from the FIFO through the system side interface. Valid and errored packet counts are provided for performance monitoring. The S/UNI-TETRA Packet over SONET/SDH implementation is flexible enough to support several link layer protocols, including HDLC, PPP and Frame Relay.

The S/UNI-TETRA PM5351 transmits SONET/SDH streams using a bit serial interface and formats section, line, and path overhead appropriately. It synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion of PM5351 (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (M1, G1) are also inserted. The S/UNI-TETRA generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell or POS frame payload. Line and Section DCC ports of PM5351 are available for direct insertion and extraction of DCC data. The S/UNI-TETRA PM5351 also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

When PM5351 used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide Utopia Level 2 datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-TETRA provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

When used to implement a Packet over SONET/SDH link, the S/UNI-TETRA inserts POS frames into the SONET/SDH synchronous payload envelope. Packets of PM5351 to be transmitted are written into a 256-byte FIFO through the POS-PHY System Interface. POS Frames are built by inserting the flags, Control Escape characters and the FCS fields. Either the CRC-CCITT or CRC-32 can be computed and added to the frame. Several counters are provided for performance monitoring.

No line rate clocks are required directly by the S/UNI-TETRA as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz reference clock. The S/UNI-TETRA outputs a differential TTL (externally coverted to PECL) line data (TXD+/-). Optionally, the S/UNI-TETRA can also output a differential TTL (externally converted to PECL) transmit line rate clock (TXC+/-). The S/UNITETRA also provides a WAN Synchronization controller that can be used to control an external VCXO in order to fully meet Bellcore GR-253-CORE jitter, wander, holdover and stability requirements.

The S/UNI-TETRA is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-TETRA also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. The S/UNI-TETRA is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible outputs and is packaged in a 304 pin SBGA package.