PM5349

1.1 General
` Single chip QUAD ATM User-Network Interface operating at 155.52 Mbit/s.
` Implements the ATM Forum User Network Interface Specification and the ATM physical layer for Broadband ISDN according to CCITT Recommendation I.432.
` Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with on-chip clock and data recovery and clock synthesis.
` Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter criteria.
` Fully implements the ATM Forum's Utopia Level 2 Specification with Multi- PHY addressing and parity support.
` Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.
` Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
` Low power 3.3V CMOS with PECL and TTL compatible inputs and CMOS/TTL outputs, with 5V tolerance inputs (system side interface is 3.3V only).
` Industrial temperature range (-40°C to +85°C).
` 304 pin Super BGA package.
1.2 The SONET Receiver
` Provides a serial interface at 155.52 Mbit/s.
` Recovers the clock and data.
` Frames to and de-scrambles the recovered stream.
` Detects signal degrade (SD) and signal fail (SF) threshold crossing alarms based on received B2 errors.
` Captures and debounces the synchronization status (S1) byte in a readable register.
` Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure.
` Counts received section BIP-8 (B1) errors, received line BIP-24 (B2) errors, line far end block errors (FEBE), received path BIP-8 (B3) errors and path far end block errors (FEBE).
` Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (LAIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (PAIS), path remote defect indication (PRDI) and path extended remote defect indicator (PERDI).
` Interprets the received payload pointer (H1, H2) and extracts the STS-3c (STM-1) synchronous payload envelope and path overhead.
` Provides individual divide by 8 recovered clocks (19.44 MHz) for each channel.
` Provides individual 8KHz receive frame pulses for each channel.
1.3 The Receive ATM Processor
` Extracts ATM cells from the received STS-3c (STM-1) synchronous payload envelope using ATM cell delineation.
` Provides ATM cell payload de-scrambling.
` Performs header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering.
` Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
` Counts number of received cells, idle cells, errored cells and dropped cells.
` Provides a synchronous 8-bit wide, four-cell FIFO buffer.
1.4 The SONET Transmitter
` Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference.
` Provides a differential TTL serial interface (can be adapted to PECL levels) at 155.52 Mbit/s.
` Provides a single transmit frame pulse input across the four channels to align the transport frames to a system reference.
` Provides a single transmit byte clock (divide by eight of the synthesized line rate clock) to provide a timing reference for the transmit outputs.
` Optionally inserts register programmable APS (K1, K2) and synchronization status (S1) bytes.
` Optionally inserts path alarm indication signal (PAIS), path remote defect indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI).
` Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line BIP-24 codes (B2), line far end block error (M1) indications, and section BIP-8 codes (B1) to allow performance monitoring at the far end.
` Scrambles the transmitted STS-3c (STM-1) stream and inserts the framing bytes (A1, A2).
` Inserts ATM cells into the transmitted STS-3c (STM-1) synchronous payload envelope.
1.5 The Transmit ATM Processor
` Provides idle/unassigned cell insertion.
` Provides HCS generation/insertion, and ATM cell payload scrambling.
` Counts number of transmitted and idle cells.
` Provides a synchronous 8-bit wide, four cell FIFO buffer.

The PM5349 S/UNI-QUAD SATURN User Network Interface is a monolithic integrated circuit that implements four channel SONET/SDH processing and ATM mapping functions at the STS-3c (STM-1) 155.52 Mbit/s rate.

The PM5349 S/UNI-QUAD receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. It performs framing (A1, A2), de-scrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M1, G1) are also accumulated. The PM5349 S/UNI-QUAD interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload.

The PM5349 S/UNI-QUAD frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM PM5349 cell payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a 16-bit wide Utopia level 2 compliant datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes.

The PM5349 S/UNI-QUAD transmits SONET/SDH streams using a bit serial interface and formats section, line, and path overhead appropriately. PM5349 synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (M1, G1) are also inserted. The PM5349 S/UNI-QUAD generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. The S/UNI-QUAD also supports the insertion of a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications.

ATM cells are written to an internal four cell FIFO using a 16-bit wide Utopia Level 2 datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-QUAD provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed.

No line rate clocks are required directly by the S/UNI-QUAD as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz reference clock. The S/UNI-QUAD outputs a differential TTL (externally coverted to PECL) line data (TXD+/-).

The S/UNI-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-QUAD also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. The S/UNI-QUAD is implemented in low power, +3.3 Volt, CMOS technology. It has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible outputs and is packaged in a 304 pin SBGA package.