PM5344

· Monolithic SONET/SDH Path Terminating Transceiver that terminates the path overhead of one or three STS-1 (AU3) paths or a single STS-3c (AU4) path.
· Maps one or three STS-1 (AU3) payloads or a single STS-3c (AU4) payload to system timing reference, accommodating plesiochronous timing offsets between the references through pointer processing.
· Operates at 19.44 MHz or 6.48 MHz, processing a duplex 19.44 Mbyte/s or 6.48 Mbyte/s data stream.
· Supports line loopback from line side receive stream to transmit stream and diagnostic loopback from ADD bus interface to DROP bus interface.
· Operates in conjunction with the PM5343 STXC, or with the PM5312 STTX and PM5318 SIPO to form a complete physical interface up to photonics.
· Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring.
· Low power, +5 Volt, CMOS technology, TTL compatible inputs and outputs.
· 160 pin plastic quad flat pack (PQFP) package.
1.1 The receiver section:
· Operates in STS-3 (AU3) or STS-3c (AU4) mode.
· Accepts a byte serial line side multiplex of three STS-1 (AU3) streams or a single STS-3c (AU4) stream, interprets the STS (AU) pointer bytes (H1, H2, and H3), and extracts the synchronous payload envelope(s) and inserts the synchronous payload envelope(s) into a bus referenced to system timing, using pointer processing.
· Extracts and processes the three STS-1 (AU3) path overhead streams or the single STS-3c (AU4) path overhead stream.
· Detects loss of pointer (LOP).
· Detects loss of tributary multiframe (LOM).
· Detects path alarm indication signal (AIS).
· Detects path FERF alarm.
· Extracts and serializes the entire path overhead from the three STS-1 (AU3) or single STS-3c (AU4) stream. Identifies the positions of the path overhead bytes in the serialized streams.
· Extracts the path signal label (C2) byte into an internal register and detects for path signal label unstable and for signal label mismatch with the expected signal label that is downloaded by the microprocessor.
· Extracts the 64 byte or 16 byte path trace (J1) message into an internal register bank.
· Detects for unstable path trace message and mismatch with the expected
path trace message that is downloaded by the microprocessor.
· Detects received path BIP-8 and counts received path BIP-8 errors for performance monitoring purposes. Path BIP-8 errors are also available on an output pin. BIP-8 errors are selectable to be treated on a bit basis or block basis.
· Counts received path far end block errors (FEBEs) for performance monitoring purposes.
· Extracts the three STS-1 (AU3) payloads or single STS-3c (AU4) payload and presents it on a byte serial bus.
· Supports Telecombus interfaces by indicating the location of the STS identification byte (C1), the path trace byte(s) (J1), the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the byte serial stream. Also generates bus parity.
· Accomodates phase and frequency differences between the receive stream and the DROP bus via pointer adjustments in the DROP bus.
· Supports tandem connection origination applications by sourcing a new tandem path maintenance byte (Z5) reporting the received BIP-8 errors and the data link message and correcting subsequent path BIP-8 bytes (B3) to reflect the change in Z5.
· Supports tandem connection termination applications by accumulating the incoming error count (IEC) and extracting the tandem connection data link carried in the tandem path maintenance byte (Z5).
· Maintains existing pointer value during incoming signal failures in tandem path terminating mode.
· Maintains the existing tributary multiframe sequence on the H4 byte until a new phase alignment has been verified.
· Provides a "Telecombus" line side receive interface when path termination is
done by an upstream device.
· Provides a serial alarm port communication of FEBE and path FERF alarms to the transmit stream in the returning direction.
1.2 The transmitter section:
· Operates in STS-1 (AU3) or STS-3c (AU4) mode.
· Accepts a byte serial multiplex of three STS-1 (AU3) streams or an STS-3c (AU4) stream, extracts the synchronous payload envelope(s) and inserts the synchronous payload envelope(s) with a generated pointer into the transmit system, using pointer processing.
· Supports system side "Telecombus" interfaces by accepting indications of the location of the STS identification byte (C1), the path trace byte(s) (J1), the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes in the byte serial stream.
· Provides line side "Telecombus" interface on the transmit stream indicating the location of the STS identification byte (C1), the path trace byte(s) (J1), the first tributary overhead byte(s) (V1), and all synchronous payload envelope bytes.
· Accomodates phase and frequency differences between the ADD bus and the transmit stream via pointer adjustments in the transmit stream.
· Optionally inserts STS path alarm indication signal (AIS).
· Optionally inserts STS path FERF alarm.
· Inserts the path overhead bytes in the three STS-1 (AU3) or single STS-3c (AU4) stream. The path overhead bytes may be sourced from internal registers or from bit serial path overhead input streams. Path overhead insertion may also be disabled.
· Optionally calculates and inserts path BIP-8 error detection codes.
· Optionally inserts the path FEBE count into the path status byte (G1) based on BIP-8 errors detected in the receive path.
· Inserts the path signal label (C2) byte from an internal register.
· Inserts the 64 byte or 16 byte path trace (J1) message from an internal register bank.
· Errors may be inserted in the path BIP8 byte (B3) for diagnostic purposes.
· Optionally inserts all-ones payload data for unequipped operations.
· Optionally generates cyclical tributary multiframe pattern.
· Supports in-band error reporting of BIP-8 and path alarms in the path status byte (G1).

The PM5344 SPTX SONET/SDH Path Terminating Transceiver is a monolithic integrated circuit that implements payload alignment and path termination for three PM5344 STS-1 (AU3) paths or a single STS-3c (AU4) path, mapping these payloads onto a Telecombus-like system backplane.

The PM5344 SPTX operates in conjunction with the PM5343 STXC SONET/SDH Transport Terminating Transceiver to form a complete system for terminating section, line, and path overhead of a SONET STS-3 (SDH STM-1) or SONET STS-1 electrical interface. Four SPTX devices operate in conjunction with the PM5712 SLIM SONET/SDH Line Interface Module to form a complete system for terminating section, line, and path overhead of a SONET STS-12 (SDH STM-4) electrical interface.

The PM5344 SPTX provides receive path termination for a SONET STS-1, STS-3 or STS- 3c stream, or equivalently, an AU3 or an SDH STM-1 stream carrying three AU3s or one AU4. The PM5344 SPTX interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope (virtual container). The extracted SPE (VC) is placed on a Telecombus DROP bus. Frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the received data stream and the DROP bus are accommodated by pointer adjustments in the DROP bus. In addition to its basic processing of the received SONET/SDH overhead, the PM5344 SPTX provides convenient access to all overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired.

The PM5344 SPTX provides transmit path origination for a SONET STS-1, STS-3 or STS- 3c stream, or equivalently, an AU3 or an SDH STM-1 stream carrying three AU3s or one AU4. The SPTX generates the transmit payload pointers (H1, H2) and inserts the synchronous payload envelope (virtual container) from a Telecombus ADD bus into the transmit stream. Frequency offsets (e.g., due to plesiochronous network boundaries, or the loss of a primary reference timing source) and phase differences (due to normal network operation) between the transmit data stream and the ADD bus are accommodated by pointer adjustments in the transmit stream. In addition to its basic processing of the transmit PM5344 SONET/SDH overhead, the SPTX provides convenient access to all overhead bytes, which are inserted serially on lower rate interfaces, allowing additional external sourcing of overhead, if desired. The PM5344 SPTX also supports the insertion of a large variety of errors into the transmit stream, such as bit interleaved parity errors, and inverted NDF flags, which are useful for system diagnostics and tester applications.The SPTX supports in-band error reporting where the path status byte (G1) inserted in the DROP bus reflects the number of BIP-8 errors detected and the path FERF status. The PM5344 SPTX can be programmed to pass the path status byte on the ADD bus through unmodified. This feature allows the transmit path processor to be located remotely to the receive processor without having to incur the cost of routing an alarm port.

The SPTX supports tandem connection termination applications where the tandem connection maintenance byte (Z5) carries the incoming BIP-8 error count, a tandem data link, and a path AIS code. The incoming error count is accumulated and the receive data link is serialized for external processing. A new data link can be inserted from a low speed serial input. An incoming signal failure alarm (ISF) is used to convey path AIS in place of all-ones in the pointer (H1, H2).

The SPTX maintains a large number of statistics for performance monitoring purposes. BIP-8 errors, and tandem path incoming error counts are accumulated. In addition, the SPTX is selectable to accumulate positive and negative pointer justifications that it receives or justifications that it generates on the DROP bus. It also accumulates positive and negative pointer justifications in the transmit stream. Excessive justifications may be indicative of clock synchronization failures.

In STS-3c, STS-3 (AU4, three AU3s) applications, no auxiliary high speed clocks are required as the SPTX operates from a set of plesiochronous 19.44 MHz clocks. In STS-1 (single AU3) applications, the SPTX operates from a set of plesiochronous 6.48 MHz clocks. The SPTX is configured, controlled and monitored via a generic 8-bit microprocessor bus interface.

The SPTX is implemented in low power, +5 Volt, CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 160 pin PQFP package.